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S3C84BB/F84BB
8-BIT CMOS MICROCONTROLLERS USER'S MANUAL
Revision 1
Important Notice
information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. S3C84BB/F84BB 8-Bit CMOS Microcontrollers User's Manual, Revision 1 Publication Number: 20-S3-C84BB/F84BB-0800 (c) 2000 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung- Eup Yongin-City, Kyunggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(31)-209-1907 FAX: (82)-(31)-209-1899 Home Page: http://www.intl.samsungsemi.com Printed in the Republic of Korea "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
Preface
The S3C84BB/F84BB Microcontroller User's Manual is designed for application designers and programmers who are using the S3C84BB/84BB microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1, "Product Overview," is a high-level introduction to S3C84BB/F84BB with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the S3C8-series CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C84BB/F84BB interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II. Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3C-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1-3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C84BB/F84BB microcontroller. Also included in Part II are electrical, mechanical, Flash MCU, and development tools data. It has 15 chapters: Chapter 7 Clock Circuit Chapter 15 10-bit A/D Converter Chapter 8 RESET and Power-Down Chapter 16 8-bit D/A Converter Chapter 9 I/O Ports Chapter 17 Pattern Generation Module Chapter 10 Basic Timer Chapter 18 Embedded Flash Memory Interface Chapter 11 8-bit Timer A/B/C(0/1) Chapter 19 Electrical Data Chapter 12 16-bit Timer 1(0/1) Chapter 20 Mechanical Data Chapter 13 Serial I/O Port Chapter 21 Development Tools Chapter 14 UART(0/1) Two order forms are included at the back of this manual to facilitate customer order for S3C84BB/F84BB microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
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Table of Contents
Part I -- Programming Model
Chapter 1 Product Overview
S3C8-Series Microcontrollers .......................................................................................................................1-1 S3C84BB/F84BB Microcontroller..................................................................................................................1-1 Features ........................................................................................................................................................1-2 Block Diagram ...............................................................................................................................................1-3 Pin Assignment .............................................................................................................................................1-4 Pin Descriptions ............................................................................................................................................1-6 Pin Circuits ....................................................................................................................................................1-9
Chapter 2
Address Spaces
Overview........................................................................................................................................................2-1 Program Memory (ROM)...............................................................................................................................2-2 Register Architecture.....................................................................................................................................2-3 Register Page Pointer (PP) ..................................................................................................................2-5 Register Set 1 .......................................................................................................................................2-6 Register Set 2 .......................................................................................................................................2-6 Prime Register Space...........................................................................................................................2-7 Working Registers ................................................................................................................................2-8 Using The Register Pointers.................................................................................................................2-9 Register Addressing ......................................................................................................................................2-11 Common Working Register Area (C0H-CFH) .....................................................................................2-13 4-Bit Working Register Addressing ......................................................................................................2-14 8-Bit Working Register Addressing ......................................................................................................2-16 System And User Stack ................................................................................................................................2-18
Chapter 3
Addressing Modes
Overview........................................................................................................................................................3-1 Register Addressing Mode (R)......................................................................................................................3-2 Indirect Register Addressing Mode (IR) ........................................................................................................3-3 Indexed Addressing Mode (X).......................................................................................................................3-7 Direct Address Mode (DA) ............................................................................................................................3-10 Indirect Address Mode (IA) ...........................................................................................................................3-12 Relative Address Mode (RA).........................................................................................................................3-13 Immediate Mode (IM) ....................................................................................................................................3-14
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Table of Contents (Continued)
Chapter 4 Control Registers
Overview .............................................................................................................................................. 4-1
Chapter 5
Interrupt Structure
Overview ....................................................................................................................................................... 5-1 Interrupt Types ..................................................................................................................................... 5-2 S3C84BB/F84BB Interrupt Structure ................................................................................................... 5-3 Interrupt Vector Addresses .................................................................................................................. 5-5 Enable/Disable Interrupt Instructions (EI, DI) ...................................................................................... 5-7 System-Level Interrupt Control Registers............................................................................................ 5-7 Interrupt Processing Control Points ..................................................................................................... 5-8 Peripheral Interrupt Control Registers ................................................................................................. 5-9 System Mode Register (SYM) ............................................................................................................. 5-10 Interrupt Mask Register (IMR) ............................................................................................................. 5-11 Interrupt Priority Register (IPR)............................................................................................................ 5-12 Interrupt Request Register (IRQ)......................................................................................................... 5-14 Interrupt Pending Function Types........................................................................................................ 5-15 Interrupt Source Polling Sequence ...................................................................................................... 5-16 Interrupt Service Routines ................................................................................................................... 5-16 Generating Interrupt Vector Addresses ............................................................................................... 5-17 Nesting of Vectored Interrupts ............................................................................................................. 5-17
Chapter 6
Instruction Set
Overview ....................................................................................................................................................... 6-1 Data Types........................................................................................................................................... 6-1 Register Addressing............................................................................................................................. 6-1 Addressing Modes ............................................................................................................................... 6-1 Flags Register (FLAGS)....................................................................................................................... 6-6 Flag Descriptions ................................................................................................................................. 6-7 Instruction Set Notation........................................................................................................................ 6-8 Condition Codes .................................................................................................................................. 6-12 Instruction Descriptions........................................................................................................................ 6-13
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Table of Contents (Continued)
Part II Hardware Descriptions
Chapter 7 Clock Circuit
Overview........................................................................................................................................................7-1 System Clock Circuit ............................................................................................................................7-1 Clock Status During Power-Down Modes ............................................................................................7-2 System Clock Control Register (CLKCON) ..........................................................................................7-3
Chapter 8
RESET and Power-Down
System Reset ................................................................................................................................................8-1 Overview...............................................................................................................................................8-1 Normal Mode Reset Operation.............................................................................................................8-1 Hardware Reset Values........................................................................................................................8-2 Power-Down Modes ......................................................................................................................................8-5 Stop Mode ............................................................................................................................................8-5 Idle Mode ..............................................................................................................................................8-6
Chapter 9
I/O Ports
Overview........................................................................................................................................................9-1 Port Data Registers ..............................................................................................................................9-2 Port 0 ....................................................................................................................................................9-3 Port 1 ....................................................................................................................................................9-5 Port 2 ....................................................................................................................................................9-7 Port 3 ....................................................................................................................................................9-10 Port 4 ....................................................................................................................................................9-13 Port 5 ....................................................................................................................................................9-17 Port 6 ....................................................................................................................................................9-20 Port 7 ....................................................................................................................................................9-21 Port 8 ....................................................................................................................................................9-23
Chapter 10
Basic Timer
Overview........................................................................................................................................................10-1 Basic Timer (BT)...................................................................................................................................10-1 Basic Timer Control Register (BTCON) ...............................................................................................10-1 Basic Timer Function Description.........................................................................................................10-3
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Table of Contents (Continued)
Chapter 11 8-bit Timer A/B/C(0/1)
8-Bit Timer A................................................................................................................................................. 11-1 Overview .............................................................................................................................................. 11-1 Function Description ............................................................................................................................ 11-2 Timer A Control Register (TACON) ..................................................................................................... 11-3 Block Diagram...................................................................................................................................... 11-4 8-Bit Timer B................................................................................................................................................. 11-5 Overview .............................................................................................................................................. 11-5 Block Diagram...................................................................................................................................... 11-5 Timer B Control Register (TBCON) ..................................................................................................... 11-6 Timer B Pulse Width Calculations ....................................................................................................... 11-7 8-Bit Timer C (0/1) ........................................................................................................................................ 11-11 Overview .............................................................................................................................................. 11-11 Timer C(0/1) Control Register (TCCON0, TCCON1) .......................................................................... 11-12 Block Diagram...................................................................................................................................... 11-13
Chapter 12
16-bit Timer 1(0/1)
Overview ....................................................................................................................................................... 12-1 Function Description ............................................................................................................................ 12-2 Timer 1(0/1) Control Register (T1CON0, T1CON1) ............................................................................ 12-3 Block Diagram...................................................................................................................................... 12-6
Chapter 13
Serial I/O Port
Overview ....................................................................................................................................................... 13-1 Programming Procedure...................................................................................................................... 13-1 SIO Control Register (SIOCON) .......................................................................................................... 13-2 SIO Prescaler Register (SIOPS).......................................................................................................... 13-3 Block Diagram...................................................................................................................................... 13-3 Serial I/O Timing Diagrams.................................................................................................................. 13-4
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Table of Contents (Continued)
Chapter 14 UART(0/1)
Overview........................................................................................................................................................14-1 Programming Procedure ......................................................................................................................14-1 Uart Control Register (UARTCON0, UARTCON1) ..............................................................................14-2 Uart Interrupt Pending Register (UARTPND).......................................................................................14-3 Uart Data Register (UDATA0, UDATA1)..............................................................................................14-4 Uart Baud Rate Data Register (BRDATA0, BRDATA1).......................................................................14-4 Baud Rate Calculations ........................................................................................................................14-4 Block Diagram ...............................................................................................................................................14-6 Uart Mode 0 Function Description ........................................................................................................14-7 Uart Mode 1 Function Description ........................................................................................................14-8 Uart Mode 2 Function Description ........................................................................................................14-9 Uart Mode 3 Function Description ........................................................................................................14-10 Serial Communication for Multiprocessor Configurations ....................................................................14-11
Chapter 15
10-bit A/D Converter
Overview........................................................................................................................................................15-1 Function Description......................................................................................................................................15-1 Conversion Timing................................................................................................................................15-2 A/D Converter Control Register (ADACON).........................................................................................15-2 Internal Reference Voltage Levels .......................................................................................................15-4 Conversion Timing................................................................................................................................15-4 Internal A/D Conversion Procedure......................................................................................................15-5
Chapter 16
10-bit D/A Converter
Overview........................................................................................................................................................16-1 D/A Conversion Control Register (ADACON) ......................................................................................16-2 D/A Conversion Data Register (DADATA) ...........................................................................................16-2 Block Diagram ......................................................................................................................................16-3
Chapter 17
Pattern Generation Module
Overview........................................................................................................................................................17-1 Pattern Gneration Flow.........................................................................................................................17-1
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Table of Contents (Continued)
Chapter 18 Embedded FLASH Memory Interface
Overview ....................................................................................................................................................... 18-1 FLASH Memory Control Registers ............................................................................................................... 18-3 Sector Erase ................................................................................................................................................. 18-5 Programming ................................................................................................................................................ 18-9 Data Protection ............................................................................................................................................. 18-12
Chapter 19
Electrical Data
Overview .............................................................................................................................................. 19-1
Chapter 20
Mechanical Data
Overview .............................................................................................................................................. 20-1
Chapter 21
Development Tools
Overview ....................................................................................................................................................... 21-1 Shine .................................................................................................................................................... 21-1 SAMA Assembler ................................................................................................................................. 21-1 SASM88 ............................................................................................................................................... 21-1 HEX2ROM ........................................................................................................................................... 21-1 Target Boards ...................................................................................................................................... 21-1 TB84BB Target Board.......................................................................................................................... 21-3 IDLE LED ............................................................................................................................................. 21-5 STOP LED ........................................................................................................................................... 21-5
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S3C84BB/F84BB MICROCONTROLLER
List of Figures
Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 Title Page Number
S3C84BB/F84BB Block Diagram ...............................................................................1-3 S3C84BB/F84BB Pin Assignment (80-QFP)..............................................................1-4 S3C84BB/F84BB Pin Assignment (80-TQFP) ...........................................................1-5 Pin Circuit Type B (RESETB) ......................................................................................1-9 Pin Circuit Type C.......................................................................................................1-9 Pin Circuit Type D (P0, P1, P2 except P2.3, P3, P8 except P8.4, P8.5) ...................1-10 Pin Circuit Type D-1 (P4, P8.4, P8,5).........................................................................1-10 Pin Circuit Type D-2 (P2.3).........................................................................................1-11 Pin Circuit Type E (ADC0-ADC7)...............................................................................1-11 Pin Circuit Type F (P6) ...............................................................................................1-12 Pin Circuit Type G (P5.7-P5.4) ...................................................................................1-12 Program Memory Address Space ..............................................................................2-2 Internal Register File Organization.............................................................................2-4 Register Page Pointer (PP) ........................................................................................2-5 Set 1, Set 2, Prime Area Register ..............................................................................2-7 8-Byte Working Register Areas (Slices) .....................................................................2-8 Contiguous 16-Byte Working Register Block .............................................................2-9 Non-Contiguous 16-Byte Working Register Block .....................................................2-10 16-Bit Register Pair ....................................................................................................2-11 Register File Addressing ............................................................................................2-12 Common Working Register Area................................................................................2-13 4-Bit Working Register Addressing ............................................................................2-15 4-Bit Working Register Addressing Example .............................................................2-15 8-Bit Working Register Addressing ............................................................................2-16 8-Bit Working Register Addressing Example .............................................................2-17 Stack Operations ........................................................................................................2-18 Register Addressing ...................................................................................................3-2 Working Register Addressing.....................................................................................3-2 Indirect Register Addressing to Register File.............................................................3-3 Indirect Register Addressing to Program Memory .....................................................3-4 Indirect Working Register Addressing to Register File ..............................................3-5 Indirect Working Register Addressing to Program or Data Memory ..........................3-6 Indexed Addressing to Register File ..........................................................................3-7 Indexed Addressing to Program or Data Memory with Short Offset ..........................3-8 Indexed Addressing to Program or Data Memory......................................................3-9 Direct Addressing for Load Instructions .....................................................................3-10 Direct Addressing for Call and Jump Instructions ......................................................3-11 Indirect Addressing.....................................................................................................3-12 Relative Addressing....................................................................................................3-13 Immediate Addressing................................................................................................3-14
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List of Figures (Continued)
Figure Number 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 7-1 7-2 7-3 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 Title Page Number
Register Description Format ...................................................................................... 4-4 S3C8-Series Interrupt Types ..................................................................................... 5-2 S3C84BB/F84BB Interrupt Structure ......................................................................... 5-4 ROM Vector Address Area ........................................................................................ 5-5 Interrupt Function Diagram ........................................................................................ 5-8 System Mode Register (SYM) ................................................................................... 5-10 Interrupt Mask Register (IMR) ................................................................................... 5-11 Interrupt Request Priority Groups .............................................................................. 5-12 Interrupt Priority Register (IPR) ................................................................................. 5-13 Interrupt Request Register (IRQ)............................................................................... 5-14 System Flags Register (FLAGS) ............................................................................... 6-6 Main Oscillator Circuit (Crystal or Ceramic Oscillator) .............................................. 7-1 System Clock Circuit Diagram ................................................................................... 7-2 System Clock Control Register (CLKCON) ............................................................... 7-3 Port 0 Control Register (P0CON) .............................................................................. 9-4 Port 1 Control Register (P1CON) .............................................................................. 9-6 Port 2 High-Byte Control Register (P2CONH)........................................................... 9-8 Port 2 Low-Byte Control Register (P2CONL) ............................................................ 9-9 Port 3 High-Byte Control Register (P3CONH)........................................................... 9-11 Port 3 Low-Byte Control Register (P3CONL) ............................................................ 9-12 Port 4 High-Byte Control Register (P4CONH)........................................................... 9-14 Port 4 Low-Byte Control Register (P4CONL) ............................................................ 9-15 Port 4 Interrupt Control Register (P4INT) .................................................................. 9-16 Port 4 Interrupt Pending Register (P4INTPND)......................................................... 9-16 Port 5 High-Byte Control Register (P5CONH)........................................................... 9-18 Port 5 Low-Byte Control Register (P5CONL) ............................................................ 9-19 Port 7 Control Register (P7CON) .............................................................................. 9-22 Port 8 High-Byte Control Register (P8CONH)........................................................... 9-24 Port 8 Low-Byte Control Register (P8CONL) ............................................................ 9-25 Port 8 Interrupt Pending Register (P8INTPND)......................................................... 9-26
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List of Figures (Continued)
Page Number 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 12-1 12-2 12-3 13-1 13-2 13-3 13-4 13-5 13-6 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 15-1 15-2 15-3 15-4 15-5 16-1 16-2 16-3 Title Page Number
Basic Timer Control Register (BTCON) .....................................................................10-2 Basic Timer Block Diagram ........................................................................................10-4 Timer A Control Register (TACON)............................................................................11-3 Timer A Functional Block Diagram.............................................................................11-4 Timer B Functional Block Diagram.............................................................................11-5 Timer B Control Register (TBCON)............................................................................11-6 Timer B Data Registers (TBDATAH, TBDATAL) .......................................................11-6 Timer B Output Flip-Flop Waveforms in Repeat Mode ..............................................11-8 Timer C(0/1) Control Register (TCCON0, TCCON1) .................................................11-12 Timer C(0/1) Functional Block Diagram .....................................................................11-13 Timer 1(0/1) Control Register (T1CON0, T1CON1)...................................................12-4 Timer A and Timer 1(0/1) Pending Register (TINTPND) ...........................................12-5 Timer 1(0/1) Functional Block Diagram......................................................................12-6 SIO Module Control Register (SIOCON)....................................................................13-2 SIO Prescaler Register (SIOPS) ................................................................................13-3 SIO Functional Block Diagram ...................................................................................13-3 SIO Timing in Transmit/Receive Mode (Tx at falling edge, SIOCON.4=0) ................13-4 SIO Timing in Transmit/Receive Mode (Tx at rising edge, SIOCON.4=1).................13-4 SIO Timing in Receive-Only Mode (Rising edge start) ..............................................13-5 UART Control Register (UARTCON0, UARTCON1) .................................................14-2 UART Interrupt Pending Register (UARTPND)..........................................................14-3 UART Data Register (UDATA0, UDATA1).................................................................14-4 UART Baud Rate Data Register (BRDATA0, BRDATA1)..........................................14-4 UART Functional Block Diagram................................................................................14-6 Timing Diagram for UART Mode 0 Operation ............................................................14-7 Timing Diagram for UART Mode 1 Operation ............................................................14-8 Timing Diagram for UART Mode 2 Operation ............................................................14-9 Timing Diagram for UART Mode 3 Operation ............................................................14-10 Connection Example for Multiprocessor Serial Data Communications .....................14-12 A/D Converter Control Register (ADACON)...............................................................15-2 A/D Converter Data Register (ADDATAH, ADDATAL) ..............................................15-3 A/D Converter Circuit Diagram...................................................................................15-3 A/D Converter Timing Diagram ..................................................................................15-4 Recommended A/D Converter Circuit Highest Absolute Accuracy............................15-5 D/A Converter Control Register (ADACON)...............................................................16-2 D/A Converter Data Register (DADATA)....................................................................16-2 D/A Converter Circuit Diagram...................................................................................16-3
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List of Figures (Concluded)
Page Number 17-1 17-2 17-3 18-1 18-2 18-3 18-4 18-5 19-1 19-2 19-3 19-4 19-5 19-6 20-1 20-2 21-1 21-2 21-3 21-4 Title Page Number
Pattern Generation Flow ............................................................................................ 17-1 PG Control Register (PGCON) .................................................................................. 17-2 Pattern Generation Circuit Diagram........................................................................... 17-2 Flash Memory Control Register (FMCON) ................................................................ 18-3 Flash Memory User Programming Enable Register (FMUSR).................................. 18-3 Sectors in User Program Mode ................................................................................. 18-5 Sectors Erase Wave Form......................................................................................... 18-6 Program Wave Form.................................................................................................. 18-9 Input Timing for External Interrupts (Ports 4, Port 8.5, Port 8.6) ............................... 19-5 Input Timing for RESET .............................................................................................. 19-5 Stop Mode Release Timing Initiated by RESET......................................................... 19-6 Stop Mode Release Timing Initiated by Interrupts..................................................... 19-7 Clock Timing Measurement at XIN ............................................................................ 19-11 Operating Voltage Range .......................................................................................... 19-11 S3C84BB/F84BB 80-QFP Standard Package Dimensions(in Millimeters) ............... 20-1 S3C84BB/F84BB 80-TQFP Standard Package Dimensions(in Millimeters)............. 20-2 SMDS Product Configuration (SMDS2+)................................................................... 21-2 TB84BB Target Board Configuration ......................................................................... 21-3 40-Pin Connectors for TB84BB (S3C84BB, 80-QFP Package) ................................ 21-6 TB84BB Cable for 80-QFP Adapter........................................................................... 21-6
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List of Tables
Table Number 1-1 2-1 4-1 4-2 4-3 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 8-1 8-2 8-3 9-1 9-2 14-1 16-1 Title Page Number
S3C84BB/F84BB Pin Descriptions (80-QFP) ............................................................1-6 S3C84BB/F84BB Register Type Summary................................................................2-3 Set 1 Registers ...........................................................................................................4-1 Set 1, Bank 0 Registers..............................................................................................4-2 Set 1, Bank 1 Registers..............................................................................................4-3 Interrupt Vectors .........................................................................................................5-6 Interrupt Control Register Overview ...........................................................................5-7 Interrupt Source Control and Data Registers .............................................................5-9 Instruction Group Summary........................................................................................6-2 Flag Notation Conventions .........................................................................................6-8 Instruction Set Symbols..............................................................................................6-8 Instruction Notation Conventions ...............................................................................6-9 Opcode Quick Reference ...........................................................................................6-10 Condition Codes .........................................................................................................6-12 S3F84BB Set 1 Register Values after RESET ............................................................8-2 S3F84BB Set 1, Bank 0 Register Values after RESET...............................................8-3 S3F84BB Set 1, Bank 1 Register Values after RESET...............................................8-4 S3C84BB/F84BB Port Configuration Overview .........................................................9-1 Port Data Register Summary......................................................................................9-2 Commonly Used Baud Rates Generated by BRDATA0, BRDATA1..........................14-5 DADATA Setting to Generate Analog Voltage ...........................................................16-3
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List of Tables (Continued)
Table Number 18-1 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 21-1 21-2 Title Page Number
Command in User Program Mode ............................................................................. 18-2 Absolute Maximum Ratings ....................................................................................... 19-2 D.C. Electrical Characteristics ................................................................................... 19-2 A.C. Electrical Characteristics ................................................................................... 19-5 Input/Output Capacitance .......................................................................................... 19-6 Data Retention Supply Voltage in Stop Mode ........................................................... 19-6 A/D Converter Electrical Characteristics ................................................................... 19-8 D/A Converter Electrical Characteristics ................................................................... 19-8 Flash Memory D.C. Electrical Characteristics ........................................................... 19-9 Flash Memory A.C. Electrical Characteristics ........................................................... 19-9 Main Oscillator Frequency (fOSC1)............................................................................. 19-10 Main Oscillator Clock Stabilization Time (tST1).......................................................... 19-10 Power Selection Settings for TB84BB ....................................................................... 21-4 Using Single Header Pins as the Input Path for External Trigger Sources ............... 21-5
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List of Programming Tips
Description Chapter 2: Address Spaces Page Number
Using the Page Pointer for RAM clear (Page 0, Page 1)..............................................................................2-5 Setting the Register Pointers ........................................................................................................................2-9 Using the RPs to Calculate the Sum of a Series of Registers ......................................................................2-10 Addressing the Common Working Register Area .........................................................................................2-14 Standard Stack Operations Using PUSH and POP ......................................................................................2-19 Chapter 11: 8-bit Timer A/B/C(0/1)
To Generate 38 kHz, 1/3Duty Signal Through P2.4 .....................................................................................11-9 To Generate a One Pulse Signal Through P2.4 ...........................................................................................11-10 Using the Timer A..........................................................................................................................................11-14 Using the Timer B..........................................................................................................................................11-15 Using the Timer C(0/1) ..................................................................................................................................11-16 Chapter 12: 16-bit Timer 1(0/1)
Using the Timer 1(0)......................................................................................................................................12-7 Chapter 13: Serial I/O Port
Use Internal Clock to Transmit and Receive Serial Data..............................................................................13-5 Chapter 15: 10-Bit A/D Converter
Configuring A/D Converter ............................................................................................................................15-6 Chapter 17: Pattern Generation Module
Using the Pattern Generation........................................................................................................................17-3 Chapter 18: Embedded FLASH Memory Interface
Sector Erase..................................................................................................................................................18-7 Programming .................................................................................................................................................18-10 Option Sector Programming(Hard Lock Protection in User Program Mode)................................................18-13
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List of Register Descriptions
Register Identifier ADACON BRDATA0 BRDATA1 BTCON CLKCON FLAGS FMCON IMR IPH IPL IPR IRQ P0CON P1CON P2CONH P2CONL P3CONH P3CONL P4CONH P4CONL P4INT P4INTPND P5CONH P5CONL P7CON P8CONH P8CONL P8INTPND PGCON Full Register Name Page Number
A/D, D/A Converter Control Register ......................................................................... 4-5 UART0 Baud Rate Data Register .............................................................................. 4-6 UART1 Baud Rate Data Register .............................................................................. 4-7 Basic Timer Control Register ..................................................................................... 4-8 System Clock Control Register .................................................................................. 4-9 System Flags Register ............................................................................................... 4-10 Flash Memory Control Register ................................................................................. 4-11 Interrupt Mask Register .............................................................................................. 4-12 Instruction Pointer (High Byte) .................................................................................. 4-13 Instruction Pointer (Low Byte) ................................................................................... 4-13 Interrupt Priority Register ........................................................................................... 4-14 Interrupt Request Register ......................................................................................... 4-15 Port 0 Control Register............................................................................................... 4-16 Port 1 Control Register............................................................................................... 4-17 Port 2 Control Register (High Byte)............................................................................ 4-18 Port 2 Control Register (Low Byte) ............................................................................ 4-19 Port 3 Control Register (High Byte)............................................................................ 4-20 Port 3 Control Register (Low Byte) ............................................................................ 4-21 Port 4 Control Register (High Byte)............................................................................ 4-22 Port 4 Control Register (Low Byte) ............................................................................ 4-23 Port 4 Interrupt Control Register ................................................................................ 4-24 Port 4 Interrupt Pending Register............................................................................... 4-25 Port 5 Control Register (High Byte)............................................................................ 4-26 Port 5 Control Register (Low Byte) ............................................................................ 4-27 Port 7 Control Register............................................................................................... 4-28 Port 8 Control Register (High Byte)............................................................................ 4-29 Port 8 Control Register (Low Byte) ............................................................................ 4-30 Port 8 Interrupt Pending Register............................................................................... 4-31 Pattern Generation Control Register.......................................................................... 4-32
S3C84BB/F84BB MICROCONTROLLER
xix
List of Register Descriptions (Continued)
Register Identifier PP RP0 RP1 SIOCON SIOPS SPH SPL SYM T1CON0 T1CON1 TACON TBCON TCCON0 TCCON1 TINTPND UARTCON0 UARTCON1 UARTPND Full Register Name Page Number
Register Page Pointer ................................................................................................4-33 Register Pointer 0 .......................................................................................................4-34 Register Pointer 1 .......................................................................................................4-34 SIO Control Register ..................................................................................................4-35 SIO Prescaler Register...............................................................................................4-36 Stack Pointer (High Byte) ...........................................................................................4-37 Stack Pointer (Low Byte) ............................................................................................4-37 System Mode Register ...............................................................................................4-38 Timer 1(0) Control Register ........................................................................................4-39 Timer 1(1) Control Register ........................................................................................4-40 Timer A Control Register ............................................................................................4-41 Timer B Control Register ............................................................................................4-42 Timer C(0) Control Register .......................................................................................4-43 Timer C(1) Control Register .......................................................................................4-44 Timer A,1 Interrupt Pending Register .........................................................................4-45 UART0 Control Register.............................................................................................4-46 UART1 Control Register.............................................................................................4-47 UART1(0) Pending Register ......................................................................................4-48
xx
S3C84BB/F84BB MICROCONTROLLER
List of Instruction Descriptions
Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LDB Full Register Name Page Number
Add with Carry............................................................................................................ 6-14 Add ............................................................................................................................. 6-15 Logical AND ............................................................................................................... 6-16 Bit AND....................................................................................................................... 6-17 Bit Compare ............................................................................................................... 6-18 Bit Complement.......................................................................................................... 6-19 Bit Reset ..................................................................................................................... 6-20 Bit Set ......................................................................................................................... 6-21 Bit OR ......................................................................................................................... 6-22 Bit Test, Jump Relative on False ............................................................................... 6-23 Bit Test, Jump Relative on True................................................................................. 6-24 Bit XOR....................................................................................................................... 6-25 Call Procedure............................................................................................................ 6-26 Complement Carry Flag ............................................................................................. 6-27 Clear ........................................................................................................................... 6-28 Complement ............................................................................................................... 6-29 Compare..................................................................................................................... 6-30 Compare, Increment, and Jump on Equal ................................................................. 6-31 Compare, Increment, and Jump on Non-Equal ......................................................... 6-32 Decimal Adjust ........................................................................................................... 6-33 Decrement.................................................................................................................. 6-35 Decrement Word ........................................................................................................ 6-36 Disable Interrupts ....................................................................................................... 6-37 Divide (Unsigned)....................................................................................................... 6-38 Decrement and Jump if Non-Zero.............................................................................. 6-39 Enable Interrupts ........................................................................................................ 6-40 Enter ........................................................................................................................... 6-41 Exit.............................................................................................................................. 6-42 Idle Operation............................................................................................................. 6-43 Increment ................................................................................................................... 6-44 Increment Word.......................................................................................................... 6-45 Interrupt Return .......................................................................................................... 6-46 Jump........................................................................................................................... 6-47 Jump Relative............................................................................................................. 6-48 Load............................................................................................................................ 6-49 Load Bit ...................................................................................................................... 6-51
S3C84BB/F84BB MICROCONTROLLER
xxi
List of Instruction Descriptions (Continued)
Instruction Mnemonic LDC/LDE LDCD/LDED LDCI/LDEI LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SB0 SB1 SBC SCF SRA SRP/SRP0/SRP1 STOP SUB SWAP TCM TM WFI XOR Full Register Name Page Number
Load Memory..............................................................................................................6-52 Load Memory and Decrement ....................................................................................6-54 Load Memory and Increment......................................................................................6-55 Load Memory with Pre-Decrement.............................................................................6-56 Load Memory with Pre-Increment ..............................................................................6-57 Load Word ..................................................................................................................6-58 Multiply (Unsigned) .....................................................................................................6-59 Next.............................................................................................................................6-60 No Operation ..............................................................................................................6-61 Logical OR ..................................................................................................................6-62 Pop from Stack ...........................................................................................................6-63 Pop User Stack (Decrementing).................................................................................6-64 Pop User Stack (Incrementing) ..................................................................................6-65 Push to Stack..............................................................................................................6-66 Push User Stack (Decrementing)...............................................................................6-67 Push User Stack (Incrementing) ................................................................................6-68 Reset Carry Flag.........................................................................................................6-69 Return .........................................................................................................................6-70 Rotate Left ..................................................................................................................6-71 Rotate Left through Carry ...........................................................................................6-72 Rotate Right................................................................................................................6-73 Rotate Right through Carry.........................................................................................6-74 Select Bank 0..............................................................................................................6-75 Select Bank 1..............................................................................................................6-76 Subtract with Carry .....................................................................................................6-77 Set Carry Flag.............................................................................................................6-78 Shift Right Arithmetic ..................................................................................................6-79 Set Register Pointer....................................................................................................6-80 Stop Operation............................................................................................................6-81 Subtract ......................................................................................................................6-82 Swap Nibbles..............................................................................................................6-83 Test Complement under Mask ...................................................................................6-84 Test under Mask .........................................................................................................6-85 Wait for Interrupt .........................................................................................................6-86 Logical Exclusive OR..................................................................................................6-87
xxii
S3C84BB/F84BB MICROCONTROLLER
S3C84BB/F84BB
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. The major CPU features are: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode released by interrupt or reset -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels.
S3C84BB/F84BB MICROCONTROLLER
The S3C84BB/F84BB single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS process, based on Samsung's latest CPU architecture. The S3C84BB is a microcontroller with a 64K-byte mask-programmable ROM embedded. The S3F84BB is a microcontroller with a 64K-byte Full-Flash ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3C84BB/F84BB by integrating the following peripheral modules with the powerful SAM8 core: -- Nine programmable I/O ports, including eight 8-bit ports and one 6-bit ports, for a total of 70 pins. -- Ten bit-programmable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog function (system reset). -- Four 8-bit timer/counter and two 16-bit timer/counter with selectable operating modes. -- Tow asynchronous UART -- One synchronous SIO -- One 8-bit D/A converter -- 8-channel A/D converter The S3C84BB/F84BB is versatile microcontroller for CD-ROM and ADC application, etc. They are currently available in 80-pin QFP and 80-pin TQFP package.
1-1
PRODUCT OVERVIEW
S3C84BB/F84BB
FEATURES
CPU
*
A/D Converter
* * *
SAM88RC CPU core
10-bit resolution Eight analog input channels 20us conversion speed at 10MHz fADC clock.
Memory
* *
2064-bytes internal register file 64K-bytes internal program memory - S3C84BB: Mask ROM - S3F84BB: Flash type memory
D/A Converter * * * 8-bit D/A Converter R/2R Resistor method One D/A output (DAOUT)
Oscillation Sources
* *
Crystal, Ceramic CPU clock divider (1/1, 1/2, 1/8, 1/16) Asynchronous UART * Full duplex 2 channels UARTs Programmable baud rate Supports serial data transmit/receive operations with 8-bit, 9-bit in UART * *
Instruction Set
* *
78 instructions IDLE and STOP instructions added for powerdown modes
Synchronous SIO Instruction Execution Time
*
* *
Programmable baud rate One synchronous serial I/O module
400 ns at 10-MHz fOSC (minimum)
Interrupts
* *
Pattern Generation Module
*
24 interrupt sources with 24 vector. 8 level, 24 vector interrupt structure
Pattern generation module triggered by timer match signal and S/W.
I/O Ports
*
Operating Temperature Range
*
Total 70 bit-programmable pins
-25C to + 85C
Timers and Timer/Counters
*
Operating Voltage Range
*
One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog-timer function. One 8-bit timer/counter (Timer A) with three operating modes; Interval mode, capture mode and PWM mode. One 8-bit timer/counter (Timer B) Carrier frequency (or PWM) generator. Two 8-bit timer with PWM mode (Timer C0,C1) Two 16-bit capture timer/counter (Timer 10,11) with two operating modes; Interval mode, Capture mode for pulse period or duty.
2.7 V to 5.5 V at 10MHz fOSC
Package Type
*
*
80 pin QFP, 80 pin TQFP
* * *
1-2
S3C84BB/F84BB
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7
AVREF
AVSS
P1.0-P1.7
Port 0 XIN XOUT RESETB
A/D
Port 1
OSC/RESETB 8-Bit Basic Timer I/O Port and Interrupt Control
Port 2
P2.0-P2.7
P2.7/TAOUT P2.6/TACAP P2.5/TACK P2.4/TBOUT P3.7/TCOUT0 P3.6/TCOUT1 P3.4/T1OUT0 P3.2/T1CAP0 P3.0/T1CK0 P3.5/T1OUT1 P3.3/T1CAP1 P3.1/T1CK1 P2.2/SCK P2.1/SI P2.0/SO P5.3/RXD0 P5.2/TXD0 P5.1/RXD1 P5.0/TXD1 P0.0~P0.7/ PG0~PG7
8-Bit Timer /CounterA,B 8-Bit Timer/ CounterC0,C1 16-Bit Timer /Counter10,11 64K-Byte ROM 2064-Byte RAM SAM88RC CPU
Port 3
P3.0-P3.7
Port 4
P4.0-P4.7/ INT0~INT7
Port 5
P5.0-P5.7
SIO/ UART0,1
Port 6 PG
P6.0-P6.7
Port 8
D/A
Port 7
P8.0-P8.5/ INT8,INT9
P2.3/ DAOUT
P7.0-P7.7/ ADC0~ADC7
Figure 1-1. S3C84BB/F84BB Block Diagram
1-3
PRODUCT OVERVIEW
S3C84BB/F84BB
PIN ASSIGNMENT
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P0.7/PG7 P0.6/PG6 P0.5/PG5 P0.4/PG4 P0.3/PG3 P0.2/PG2 P0.1/PG1 P0.0/PG0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P2.7/TAOUT P2.6/TACAP P2.5/TACK P2.4/TBPWM P2.3/DAOUT P2.2/SCK P2.1/SI P2.0/SO P5.7 P5.6/SDAT P5.5/SCLK VDD1 VSS1 XOUT XIN TEST P5.4 P5.3/RxD0 RESETB P5.2/TxD0 P5.1/RxD1 P5.0/TxD1 P3.7/TCOUT1 P3.6/TCOUT0
S3C84BB/F84BB
(80-QFP-1420C)
P8.0 P8.1 P8.2 P8.3 P8.4/INT8 P8.5/INT9 P6.0 P6.1 P6.2 P6.3 P6.4 VDD2 VSS2 P6.5 P6.6 P6.7 P7.0/ADC0 P7.1/ADC1 P7.2/ADC2 P7.3/ADC3 AVSS AVREF P7.4/ADC4 P7.5/ADC5
Figure 1-2. S3C84BB/F84BB Pin Assignment (80-QFP)
1-4
P3.5/T1OUT1 P3.4/T1OUT0 P3.3/T1CAP1 P3.2/T1CAP0 P3.1/T1CK1 P3.0/T1CK0 P4.7/INT7 P4.6/INT6 P4.5/INT5 P4.4/INT4 P4.3/INT3 P4.2/INT2 P4.1/INT1 P4.0/INT0 P7.7/ADC7 P7.6/ADC6
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S3C84BB/F84BB
PRODUCT OVERVIEW
PIN ASSIGNMENT
P8.1 P8.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P0.7/PG7 P0.6/PG6 P0.5/PG5 P0.4/PG4 P0.3/PG3 P0.2/PG2 P0.1/PG1 P0.0/PG0 P2.7/TAOUT P2.6/TACAP 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P2.5/TACK P2.4/TBPWM P2.3/DAOUT P2.2/SCK P2.1/SI P2.0/SO P5.7 P5.6/SDAT P5.5/SCLK VDD1 VSS1 XOUT XIN TEST P5.4 P5.3/RxD0 RESETB P5.2/TxD0 P5.1/RxD1 P5.0/TxD1
S3C84BB/F84BB
(80-TQFP-1212)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P8.2 P8.3 P8.4/INT8 P8.5/INT9 P6.0 P6.1 P6.2 P6.3 P6.4 VDD2 VSS2 P6.5 P6.6 P6.7 P7.0/ADC0 P7.1/ADC1 P7.2/ADC2 P7.3/ADC3 AVSS AVREF
Figure 1-3. S3C84BB/F84BB Pin Assignment (80-TQFP)
P3.7/TCOUT1 P3.6/TCOUT0 P3.5/T1OUT1 P3.4/T1OUT0 P3.3/T1CAP1 P3.2/T1CAP0 P3.1/T1CK1 P3.0/T1CK0 P4.7/INT7 P4.6/INT6 P4.5/INT5 P4.4/INT4 P4.3/INT3 P4.2/INT2 P4.1/INT1 P4.0/INT0 P7.7/ADC7 P7.6/ADC6 P7.5/ADC5 P7.4/ADC4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1-5
PRODUCT OVERVIEW
S3C84BB/F84BB
PIN DESCRIPTIONS
Table 1-1. S3C84BB/F84BB Pin Descriptions (80-QFP) Pin Name Pin Type Pin Description Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P0.0-P0.7 can be used as the PG output port (PG0-PG7). Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P2.0~P2.7 can be used as I/O for TIMERA, TIMERB, D/A, SIO Circuit Type D Pin Number 80-73 Share Pins PG0-PG7
P0.0 - P0.7 I/O
P1.0 - P1.7 I/O
D
72-65
P2.0 - P2.7 I/O
D,D-2
8-1
SO SI SCK DAOUT TBPWM TACK TACAP TAOUT T1CK0 T1CK1 T1CAP0 T1CAP1 T1OUT0 T1OUT1 TCOUT0 TCOUT1
P3.0 - P3.7 I/O
Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P3.0~P3.7 can be used as I/O for TIMERC0/C1, TIMER10/11
D
30-23
1-6
S3C84BB/F84BB
PRODUCT OVERVIEW
Table 1-1. S3C84BB/F84BB Pin Descriptions (80-QFP) (Continued) Pin Name Pin Type Pin Description Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. P4.0-P4.7 can alternately be used as inputs for external interrupts INT0-INT7, respectively (with noise filters and interrupt controller) Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P5.0~P5.3 can be used as I/O for serial por, UART0, UART1, respectively. N-channel, open-drain output only port. General-purpose digital input ports. Alternatively used as analog input pins for A/D converter modules. Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. P8.4, P8.5 can alternately be used as inputs for external interrupts INT8, INT9, respectively (with noise filters and interrupt controller) Circuit Type D-1 Pin Number 38-31 Share Pins INT0- INT7
P4.0 - P4.7 I/O
P5.0 - P5.7 I/O
G
22-17,11-9
TxD1 RxD1 TxD0 RxD0
P6.0 - P6.7 O P7.0 - P7.7 I
F E
58-54,51-49 48-45,42-39 ADC0ADC7 INT8,INT9
P8.0 - P8.5 I/O
D,D-1
64-59
1-7
PRODUCT OVERVIEW
S3C84BB/F84BB
Table 1-1. S3C84BB/F84BB Pin Descriptions (80-QFP) (Continued) Pin Name AD0 - AD7 I Pin Type Pin Description Analog input pins for A/D converter module. Alternatively used as general-purpose digital input port 7. A/D converter reference voltage and ground Serial data RxD pin for receive input and transmit output (mode 0) Serial data TxD pin for transmit output and shift clock input (mode 0) External clock input pins for timer A Capture input pins for timer A Pulse width modulation output pins for timer A Carrier frequency output pins for timer B Timer C 8-bit PWM mode output or counter match toggle output pins External clock input pins for timer 1 Capture input pins for timer 1 Timer 1 16-bit PWM mode output or counter match toggle output pins Synchronous SIO pins System reset pin (pull-up resistor: 240 k) Pull - down register connected internally Power input pins Main oscillator pins Circuit Type E Pin Number 48-45 42-39 43, 44 18, 21 20, 22 3 2 1 4 24,23 39,30 28,27 26,25 7,8,9 19 16 12,53, 13,52 15,14 Share Pins P7.0-P7.7
AVREF, AVSS RxD0, RxD1 TxD0, TxD1 TACK TACAP TAOUT TBPWM TCOUT0 TCOUT1 T1CK0 T1CK1 T1CAP0 T1CAP1 T1OUT0 T1OUT1 SI,SO,SCK RESETB TEST VDD1, VDD2, VSS1, VSS2 XIN, XOUT
I/O O I I O O O I I O I/O I I -
D D D D D D D D D D D B -
P5.3, P5.1 P5.2, P5.0 P2.5 P2.6 P2.7 P2.4 P3.6,P3.7 P3.0,P3.1 P3.2,P3.3 P3.4,P3.5 P2.1,P2.0, P2.2 -
1-8
S3C84BB/F84BB
PRODUCT OVERVIEW
PIN CIRCUITS
VDD Pull-Up Resistor In Schmitt Trigger
Figure 1-4. Pin Circuit Type B (RESETB)
VDD
Data
P-Channel Out
Output Disable
N-Channel
Figure 1-5. Pin Circuit Type C
1-9
PRODUCT OVERVIEW
S3C84BB/F84BB
VDD
Pull-up Enable Data Output Disable Pin Circuit Type C
I/O
Figure 1-6. Pin Circuit Type D (P0, P1, P2 except P2.3, P3, P8 except P8.4, P8.5)
VDD
VDD Data Output Disable Ext.INT Input Normal Noise Filter Pull-up Enable I/O
Pin Circuit Type C
Figure 1-7. Pin Circuit Type D-1 (P4, P8.4, P8.5)
1-10
S3C84BB/F84BB
PRODUCT OVERVIEW
VDD
Pull-up Enable Data Output Disable Pin Circuit Type C
I/O
TO DAC
Figure 1-8. Pin Circuit Type D-2 (P2.3)
In ADC In EN Data TO ADC
Figure 1-9. Pin Circuit Type E (ADC0-ADC7)
1-11
PRODUCT OVERVIEW
S3C84BB/F84BB
Out Data N-Channel
Figure 1-10. Pin Circuit Type F (P6)
VDD VDD Open-Drain Data P-Channel
Pull-up Enable I/O
Output Disable
N-Channel
Input Normal
Figure 1-11. Pin Circuit Type G (P5.7-P5.4)
1-12
S3C84BB/F84BB
ADDRESS SPACES
2
OVERVIEW
ADDRESS SPACES
The S3C84BB/F84BB microcontroller has two types of address space: -- Internal program memory (ROM) -- Internal register file (RAM) A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C84BB/F84BB has an internal 64-Kbyte mask-programmable ROM/FLASH ROM and 2064-byte RAM.
2-1
ADDRESS SPACES
S3C84BB/F84BB
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3C84BB has 64-Kbytes of internal mask programmable program memory. The program memory address range is therefore 0H-FFFFH (see Figure 2-1). The first 256 bytes of the ROM (0H-0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. The ROM address at which a program execution starts after a reset is 0100H.
(Decimal) 65,535 (HEX) FFFFH
64-KByte
255 Interrupt Vector Area
0FFH
0
0H
Figure 2-1. Program Memory Address Space
2-2
S3C84BB/F84BB
ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3C84BB/F84BB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In addition, set 2 is logically expanded 8 separately addressable register pages, page 0-page 7. In case of S3C84BB/F84BB the total number of addressable 8-bit registers is 2,144. Of these 2,144 registers, 16 bytes are for CPU and system control registers, 64 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 2,048 registers are for general-purpose use. You can always address set 1 register locations, regardless of which of the 8 register pages is currently selected. Set 1 locations, however, can only be addressed using direct addressing modes. The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP). Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1. Table 2-1. S3C84BB/F84BB Register Type Summary Register Type General-purpose registers (including 16-byte common working register area, the 192-byte prime register area, and the 64-byte set 2 area) CPU and system control registers Mapped clock, peripheral, I/O control, and data registers Total Addressable Bytes Number of Bytes 2,064 16 64 2,144
2-3
ADDRESS SPACES
S3C84BB/F84BB
Page 7 Page 6 Page 5 Page 4 Page 3 Set1 FFH 32 Bytes Bank 1 Bank 0 System and Peripheral Control Registers (Register Addressing Mode) FFH Page 2 Page 1 Page 0 Set 2 E0H General-Purpose Data Registers (Indirect Register, Indexed Mode, and Stack Operations) C0H BFH 256 Bytes
E0H 64 Bytes DFH System and Peripheral Control Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) C0H
D0H CFH
Page 0
192 Bytes
Prime Data Registers (All Addressing Modes)
00H
Figure 2-2. Internal Register File Organization
2-4
S3C84BB/F84BB
ADDRESS SPACES
REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 2,064-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C84BB/F84BB microcontroller, a paged register file expansion is implemented for data registers, and the register page pointer must be changed to address other pages. After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP) DFH ,Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Destination register page selection bits: 0000 ... 0111 NOTE: Destination: Page 0 ... Destination: Page 7
Source register page selection bits: 0000 ... 0111 Source: Page 0 ... Source: Page 7
In the S3C84BB/F84BB microcontroller, pages 0~7 are implemented. A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. These values should be modified to address other pages.
Figure 2-3. Register Page Pointer (PP)
PROGRAMMING TIP -- Using the Page Pointer for RAM clear (Page 0, Page 1)
LD SRP LD CLR DJNZ CLR LD LD CLR DJNZ CLR PP,#00H #0C0H R0,#0FFH @R0 R0,RAMCL0 @R0 PP,#10H R0,#0FFH @R0 R0,RAMCL1 @R0 ; Destination 0, Source 0 ; Page 0 RAM clear starts ; R0 = 00H ; Destination 1, Source 0 ; Page 1 RAM clear starts ; R0 = 00H
RAMCL0
RAMCL1
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.
2-5
ADDRESS SPACES
S3C84BB/F84BB
REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H-FFH. The upper 32-byte area of this 64-byte space (E0H-FFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H-FFH) contains 64 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0H-DFH) and a 16-byte common working register area (C0H-CFH). You can use the common working register area as a "scratch" area for data operations being performed in other areas of the register file. Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, "Addressing Modes.") REGISTER SET 2 The same 64-byte physical space that is used for set 1 locations C0H-FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For the S3C84BB/F84BB, the set 2 address range (C0H-FFH) is accessible on pages 0-7. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode. The set 2 register area is commonly used for stack operations.
2-6
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ADDRESS SPACES
PRIME REGISTER SPACE The lower 192 bytes (00H-BFH) of the S3C84BB/F84BB's eight 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages 0, or 1 you must set the register page pointer (PP) to the appropriate source and destination values.
FFH Bank 0 Set 1 Bank 1 FFH FFH
FFH F0H E0H D0H C0H
Page 7 ... Page 0 Set 2
C0H BFH
Page 0
CPU and system control General-purpose Peripheral and I/O 00H Prime Space
Figure 2-4. Set 1, Set 2, Prime Area Register
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ADDRESS SPACES
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WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers. Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area. The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: -- One working register slice is 8 bytes (eight 8-bit working registers, R0-R7 or R8-R15) -- One working register block is 16 bytes (sixteen 8-bit working registers, R0-R15) All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1. After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H-CFH).
Slice 32 11111XXX RP1 (Registers R8-R15) Each register pointer points to one 8-byte slice of the register space, selecting a total 16byte working register block. Slice 31
FFH F8H F7H F0H Set 1 Only CFH C0H
00000XXX RP0 (Registers R0-R7)
~
~
10H FH 8H 7H 0H
Slice 2 Slice 1
Figure 2-5. 8-Byte Working Register Areas (Slices)
2-8
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ADDRESS SPACES
USING THE REGISTER POINTERS After a reset, RP# point to the working register common area: RP0 points to addresses C0H-C7H, and RP1 points to addresses C8H-CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-6 and 2-7). With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You can not, however, use the register pointers to select a working register space in set 2, C0H-FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes. The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see Figure 2-6). Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements.
PROGRAMMING TIP -- Setting the Register Pointers
SRP SRP1 SRP0 CLR LD #70H #48H #0A0H RP0 RP1,#0F8H ; ; ; ; ; RP0 RP0 RP0 RP0 RP0 70H, RP1 78H no change, RP1 48H, A0H, RP1 no change 00H, RP1 no change no change, RP1 0F8H
Register File Contains 32 8-Byte Slices 00001XXX RP1 00000XXX RP0 8-Byte Slice 8-Byte Slice FH (R15) 8H 7H 0H (R0) 16-Byte Contiguous Working Register block
Figure 2-6. Contiguous 16-Byte Working Register Block
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8-Byte Slice
CFH (R15) C8H (R8) 16-Byte Non-Contiguous Working Register block 7H (R7) 0H (R0)
11001XXX RP1 00000XXX RP0
Register File Contains 32 8-Byte Slices
8-Byte Slice
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
PROGRAMMING TIP -- Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H-85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15H, respectively: SRP0 ADD ADC ADC ADC ADC #80H R0,R1 R0,R2 R0,R3 R0,R4 R0,R5 ; ; ; ; ; ; RP0 80H R0 R0 + R0 R0 + R0 R0 + R0 R0 + R0 R0 + R1 R2 + C R3 + C R4 + C R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: ADD ADC ADC ADC ADC 80H,81H 80H,82H 80H,83H 80H,84H 80H,85H ; ; ; ; ; 80H 80H 80H 80H 80H (80H) (80H) (80H) (80H) (80H) + + + + + (81H) (82H) (83H) (84H) (85H) + + + + C C C C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
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ADDRESS SPACES
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space. Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB Rn
LSB Rn+1
n = Even address
Figure 2-8. 16-Bit Register Pair
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Special-Purpose Registers Bank 1 FFH Control Registers E0H D0H C0H BFH RP1 RP0 Register Pointers System Registers CFH Bank 0
General-Purpose Register FFH
Set 2
C0H
Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). NOTE: In the S3C84BB/F84BB microcontroller, pages 0-7 are implemented. Pages 0-7 contain all of the addressable registers in the internal register file.
Prime Registers
00H Page 0-7 Register Addressing Only All Addressing Modes Page 0-7 Indirect Register, Indexed Addressing Modes
Can be pointed by Register Pointer
Figure 2-9. Register File Addressing
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ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H-CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H-CFH, as the active 16-byte working register block: RP0 C0H-C7H RP1 C8H-CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages.
FFH FFH FFH F0H E0H D0H C0H C0H BFH Set 1 FFH
Page 7 ... Page 0 Set 2
Page 0
Following a hardware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH.
~
Prime Space
~ ~
~
RP0 = RP1 =
1100 1100
0000 1000 00H
Figure 2-10. Common Working Register Area
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PROGRAMMING TIP -- Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples 1: LD SRP LD Examples 2: ADD 0C2H,40H #0C0H R2,40H 0C3H,#45H ; Invalid addressing mode!
Use working register addressing instead: ; R2 (C2H) the value in location 40H ; Invalid addressing mode!
Use working register addressing instead: SRP ADD #0C0H R3,#45H ; R3 (C3H) R3 + 45H
4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: -- The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1). -- The five high-order bits in the register pointer select an 8-byte slice of the register space. -- The three low-order bits of the 4-bit address select one of the eight registers in the slice. As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction "INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
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ADDRESS SPACES
RP0 RP1 Selects RP0 or RP1 Address OPCODE
Register pointer provides five high-order bits
4-bit address provides three low-order bits
Together they create an 8-bit register address
Figure 2-11. 4-Bit Working Register Addressing
RP0 01110 000 Selects RP0
RP1 01111 000
01110
110
Register address (76H)
R6 0110
OPCODE 1110 Instruction 'INC R6'
Figure 2-12. 4-Bit Working Register Addressing Example
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8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing. As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing. Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address, the three low-order bits of the complete address are provided by the original instruction. Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 3 ("1") selects RP1 and the five high-order bits in RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B).
RP0 RP1 Selects RP0 or RP1 Address These address bits indicate 8-bit working register addressing 8-bit logical address
1
1
0
0
Register pointer provides five high-order bits
Three low-order bits
8-bit physical address
Figure 2-13. 8-Bit Working Register Addressing
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ADDRESS SPACES
RP0 01100 000 Selects RP1
RP1 10101 000
R11 1100 1 011
8-bit address form instruction 'LD R11, R2'
10101
011
Register address (0ABH)
Specifies working register addressing
Figure 2-14. 8-Bit Working Register Addressing Example
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SYSTEM AND USER STACK
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C84BB/F84BB architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS registers are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-15.
High Address
PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt Low Address
Stack contents after a call instruction
Figure 2-15. Stack Operations User-Defined Stacks You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI, PUSHUD, POPUI, and POPUD support user-defined stack operations. Stack Pointers (SPL, SPH) Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The most significant byte of the SP address, SP15-SP8, is stored in the SPH register (D8H), and the least significant byte, SP7-SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C84BB/F84BB, the SPL must be initialized to an 8bit value in the range 00H-FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary. When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH" instead of "00H".
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PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine)
* * *
PUSH PUSH PUSH PUSH
* * *
PP RP0 RP1 R3
; ; ; ;
Stack address 0FEH Stack address 0FDH Stack address 0FCH Stack address 0FBH

PP RP0 RP1 R3
POP POP POP POP
R3 RP1 RP0 PP
; ; ; ;
R3 Stack address 0FBH RP1 Stack address 0FCH RP0 Stack address 0FDH PP Stack address 0FEH
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NOTES
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ADDRESSING MODES
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are: -- Register (R) -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Indirect Address (IA) -- Relative Address (RA) -- Immediate (IM)
3-1
ADDRESSING MODES
S3C84BB/F84BB
REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory 8-bit Register File Address One-Operand Instruction (Example)
Register File
dst OPCODE
Point to One Register in Register File Value used in Instruction Execution
OPERAND
Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File MSB Point to RP0 ot RP1
RP0 or RP1 Selected RP points to start of working register block OPERAND
Program Memory 4-bit Working Register Two-Operand Instruction (Example) Sample Instruction: ADD R1, R2 ; Where R1 and R2 are registers in the currently selected working register area. 3 LSBs Point to the Working Register (1 of 8)
dst
src
OPCODE
Figure 3-2. Working Register Addressing
3-2
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ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H-FFH in set 1 using the Indirect Register addressing mode.
Program Memory 8-bit Register File Address One-Operand Instruction (Example)
Register File
dst OPCODE
Point to One Register in Register File Address of Operand used by Instruction
ADDRESS
Value used in Instruction Execution
OPERAND
Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address
Figure 3-3. Indirect Register Addressing to Register File
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INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory Example Instruction References Program Memory REGISTER PAIR Points to Register Pair 16-Bit Address Points to Program Memory
dst OPCODE
Program Memory Sample Instructions: CALL JP @RR2 @RR2
Value used in Instruction
OPERAND
Figure 3-4. Indirect Register Addressing to Program Memory
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ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start fo working register block
Program Memory 4-bit Working Register Address 3 LSBs Point to the Working Register (1 of 8)
~
~
dst
src
OPCODE
ADDRESS
~
Sample Instruction: OR R3, @R6 Value used in Instruction OPERAND
~
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
S3C84BB/F84BB
INDIRECT REGISTER ADDRESSING MODE (Concluded)
R e g is te r F ile M S B P o in ts to RP0 or RP1 RP0 or R P1 S e le c te d R P p o in ts to s ta rt o f w o rk in g re g is te r b lo c k N e xt 2 -b it P o in t to W o rk in g R e g is te r P a ir (1 o f 4 ) L S B S e le c ts R e g is te r P a ir 1 6 -B it a d d re s s p o in ts to p ro g ra m m e m o ry o r d a ta m e m o ry
P ro g ra m M e m o ry 4 -b it W o rk in g R e g is te r A d d re s s dst s rc OPCODE
E xa m p le In s tru c tio n R e fe re n c e s e ith e r P ro g ra m M e m o ry o r D a ta M e m o ry
P ro g ra m M e m o ry or D a ta M e m o ry
V a lu e u s e d in In s tru c tio n
OPERAND
S a m p le In s tru c tio n s : LDC LDE LDE R 5 ,@ R R 6 ; P ro g ra m m e m o ry a c c e s s R 3 ,@ R R 1 4 ; E xte rn a l d a ta m e m o ry a c c e s s @ RR4, R8 ; E xte rn a l d a ta m e m o ry a c c e s s
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
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ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H-FFH in set 1 using indexed addressing mode. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to +127. This applies to external memory accesses only (see Figure 3-8.) For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9). The only instruction that supports indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory, when implemented.
R e g is te r F ile
RP0 or RP1
V a lu e u s e d in In s tru c tio n OPERAND
+
P ro g ra m M e m o ry T w o -O p e ra n d In s tru c tio n E xa m p le B a s e A d d re s s d s t/s rc x OPCODE 3 LSBs P o in t to O n e o f th e W o rk in g R e g is te r (1 o f 8 )
IN D E X
S e le c te d R P p o in ts to s ta rt o f w o rk in g re g is te r b lo c k
S a m p le In s tru c tio n : LD R 0 , # B A S E [R 1 ] ; W h e re B A S E is a n 8 -b it im m e d ia te va lu e
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
S3C84BB/F84BB
INDEXED ADDRESSING MODE (Continued)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block
~
Program Memory 4-bit Working Register Address OFFSET dst/src x OPCODE NEXT 2 Bits Point to Working Register Pair (1 of 4) Register Pair
~
LSB Selects
+
8-Bits 16-Bits
Program Memory or Data Memory
16-Bit address added to offset
16-Bits Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + 04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
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ADDRESSING MODES
INDEXED ADDRESSING MODE (Continued)
Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block
Program Memory OFFSET 4-bit Working Register Address OFFSET src dst/src OPCODE NEXT 2 Bits Point to Working Register Pair
~
~
Register Pair 16-Bit address added to offset
LSB Selects
+
16-Bits 16-Bits
Program Memory or Data Memory
16-Bits Sample Instructions: LDC LDE R4, #1000H[RR2] R4,#1000H[RR2]
OPERAND
Value used in Instruction
; The values in the program address (RR2 + 1000H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
ADDRESSING MODES
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DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE
LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory
Sample Instructions: LDC LDE R5,1234H R5,1234H ; ; The values in the program address (1234H) are loaded into register R5. Identical operation to LDC example, except that external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
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ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Memory Address Used Upper Address Byte Lower Address Byte OPCODE
Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
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INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode. Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.
Program Memory
Next Instruction
LSB Must be Zero Current Instruction dst OPCODE
Lower Address Byte Upper Address Byte
Program Memory Locations 0-255
Sample Instruction: CALL #40H ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
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ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current PC Value
+
Signed Displacement Value
Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
Figure 3-13. Relative Addressing
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S3C84BB/F84BB
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
S3C84BB/F84BB
CONTROL REGISTERS
CONTROL REGISTERS
OVERVIEW
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3C84BB/F84BB register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and PowerDown." Table 4-1. Set 1 Registers Register Name Timer B control register Timer B data register (high byte) Timer B data register (low byte) Basic timer control register Clock control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer Mnemonic TBCON TBDATAH TBDATAL BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP Decimal 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 Hex D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
4-1
CONTROL REGISTERS
S3C84BB/F84BB
Table 4-2. Set 1, Bank 0 Registers Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Timer A/1 interrupt pending register Timer A control register Timer A data register Timer A counter register Port 8 control register (high byte) Port 8 control register (low byte) Port 8 interrupt/pending register Port 0 control register Port 1 control register Port 2 control register (high byte) Port 2 control register (low byte) Port 3 control register (high byte) Port 3 control register (low byte) Port 4 control register (high byte) Port 4 control register (low byte) Port 5 control register (high byte) Port 5 control register (low byte) Port 4 interrupt control register Port 4 interrupt/pending register Basic timer counter register Interrupt priority register Mnemonic P0 P1 P2 P3 P4 P5 P6 P7 P8 TINTPND TACON TADATA TACNT P8CONH P8CONL P8INTPND P0CON P1CON P2CONH P2CONL P3CONH P3CONL P4CONH P4CONL P5CONH P5CONL P4INT P4INTPND BTCNT IPR Decimal 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 253 255 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FDH FFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Location FCH is factory use only Location FEH is not mapped.
4-2
S3C84BB/F84BB
CONTROL REGISTERS
Table 4-3. Set 1, Bank 1 Registers Register Name SIO data register SIO Control register UART0 data register UART0 control register UART0 baud rate data register UART0,1 pending register Timer 1(0) data register (high byte) Timer 1(0) data register (low byte) Timer 1(1) data register (high byte) Timer 1(1) data register (low byte) Timer 1(0) control register Timer 1(1) control register Timer 1(0) counter register (high byte) Timer 1(0) counter register (low byte) Timer 1(1) counter register (high byte) Timer 1(1) counter register (low byte) Timer C(0) data register Timer C(1) data register Timer C(0) control register Timer C(1) control register SIO prescaler control register Port 7 control register D/A converter data register A/D, D/A converter control register A/D converter data register (high byte) A/D converter data register (low byte) UART1 data register UART1 control register UART1 baud rate data register Flash memory control register Pattern generation control register Pattern generation data register Mnemonic SIODATA SIOCON UDATA0 UARTCON0 BRDATA0 UARTPND T1DATAH0 T1DATAL0 T1DATAH1 T1DATAL1 T1CON0 T1CON1 T1CNTH0 T1CNTL0 T1CNTH1 T1CNTL1 TCDATA0 TCDATA1 TCCON0 TCCON1 SIOPS P7CON DADATA ADACON ADDATAH ADDATAL UDATA1 UARTCON1 BRDATA1 FMCON PGCON PGDATA Decimal 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W
4-3
CONTROL REGISTERS
S3C84BB/F84BB
Bit number(s) that is/are appended to the register name for bit addressing Register ID Register name
Name of individual bit or related bits
Register location Register address in the internal register file (hexadecimal)
FLAGS - System Flags Register
.7 .6 .5 .4 .3 x R/W
D5H
.2 x R/W .1 0 R
Set 1
.0 0 R/W
Bit Identifier RESET Value Read/Write Bit Addressing Mode .7
x x x x R/W R/W R/W R/W Register addressing mode only
Carry Flag (C) 0 0 Operation does not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit 7
.6
Zero Flag (Z) 0 0 Operation result is a non-zero value Operation result is zero
.5
Sign Flag (S) 0 0 Operation generates positive number (MSB = "0") Operation generates negative number (MSB = "1")
R = Read-only W = Write-only R/W = Read/write '-' = Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit)
Description of the effect of specific bit settings
RESETvalue notation: '-' = Not used 'x' = Undetermined value Bit number: MSB = Bit 7 '0' = Logic zero LSB = Bit 0 '1' = Logic one
Figure 4-1. Register Description Format
4-4
S3C84BB/F84BB
CONTROL REGISTERS
ADACON -- A/D, D/A Converter Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R
F7H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only D/A Start Enable Bit 0 1 Disable operation Start operation
.6-.4
A/D Input Pin Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
.3
End-of-Conversion Bit (Read-only) 0 1 A/D conversion opration is in progress A/D conversion opration is complete
.2-.1
Clock Source Selection Bits 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/4 fxx
.0
A/D Start or Enable Bit 0 1 Disable operation Start operation
4-5
CONTROL REGISTERS
S3C84BB/F84BB
BRDATA0 -- UART0 Baud Rate Data Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.0 .7 1 R/W .6 1 R/W .5 1 R/W .4 1 R/W .3 1 R/W
E4H
.2 1 R/W
Set 1, Bank 1
.1 1 R/W .0 1 R/W
Register addressing mode only Baud Rate Data for UART0 (note) : fxx/(16 x (BRDATA + 1))
NOTE: Refer to UARTCON0 register.
4-6
S3C84BB/F84BB
CONTROL REGISTERS
BRDATA1 -- UART1 Baud Rate Data Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.0 .7 1 R/W .6 1 R/W .5 1 R/W .4 1 R/W .3 1 R/W
FCH
.2 1 R/W
Set 1, Bank 1
.1 1 R/W .0 1 R/W
Register addressing mode only Baud Rate Data for UART1 (note) : fxx/(16 x (BRDATA + 1))
NOTE: Refer to UARTCON1 register.
4-7
CONTROL REGISTERS
S3C84BB/F84BB
BTCON -- Basic Timer Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
D3H
.2 0 R/W .1 0 R/W
Set 1
.0 0 R/W
Register addressing mode only Watchdog Timer Function Disable Code (for System Reset) 1 0 1 0 Disable watchdog timer function Enable watchdog timer function Others
.3-.2
Basic Timer Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/4096 (3) fxx/1024 fxx/128 fxx/16 (Not used)
.1
Basic Timer Counter Clear Bit (1) 0 1 No effect Clear the basic timer counter value
.0
Clock Frequency Divider Clear Bit for Basic Timer (2) 0 1 No effect Clear both clock frequency dividers
NOTES: 1. When you write a "1" to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to "0". 2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0". 3. The fxx is selected clock for system (main OSC. or sub OSC.).
4-8
S3C84BB/F84BB
CONTROL REGISTERS
CLKCON -- System Clock Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.5 .4-.3 .7 0 - .6 0 - .5 0 - .4 0 R/W .3 0 R/W
D4H
.2 0 - .1 0 -
Set 1
.0 0 -
Register addressing mode only Not used for the S3C84BB/F84BB (must keep always 0) CPU Clock (System Clock) Selection Bits (note) 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/2 fxx/1 (non-divided)
.2-.0
Not used for the S3C84BB/F84BB (must keep always 0)
NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4.
4-9
CONTROL REGISTERS
S3C84BB/F84BB
FLAGS -- System Flags Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
D5H
.2 x R/W .1 0 R
Set 1
.0 0 R/W
Register addressing mode only Carry Flag (C) 0 1 Operation does not generate a carry or underflow condition Operation generates a carry-out or underflow into high-order bit 7
.6
Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero
.5
Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V) 0 1 Operation result is +127 or -128 Operation result is > +127 or < -128
.3
Decimal Adjust Flag (D) 0 1 Add operation completed Subtraction operation completed
.2
Half-Carry Flag (H) 0 1 No carry-out of bit 3 or no underflow into bit 3 by addition or subtraction Addition generated carry-out of bit 3 or subtraction generated underflow into bit 3
.1
Fast Interrupt Status Flag (FIS) 0 1 Interrupt return (IRET) in progress (when read) Fast interrupt service routine in progress (when read)
.0
Bank Address Selection Flag (BA) 0 1 Bank 0 is selected Bank 1 is selected
4-10
S3C84BB/F84BB
CONTROL REGISTERS
FMCON -- Flash Memory Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 - .5 0 - .4 0 - .3 0 -
FDH
.2 0 -
Set 1, Bank1
.1 0 R/W .0 0 R/W
Register addressing mode only User Programming Serial Data Bit (FSDAT) 0 1 FSDA=Low (Logic 0) FSDA=High (Logic 1)
.6-.2 .1
Not used for the S3C84BB/F84BB (must keep always 0) User Programming Mode Status Bit (full-flash flag) 0 1 Not-user programming mode User programming mode
.0
User Programming Serial Clock Bit (FSCLK) 0 1 FSCLK=Low (Logic 0) FSCLK=High(Logic 1)
4-11
CONTROL REGISTERS
S3C84BB/F84BB
IMR -- Interrupt Mask Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
DDH
.2 x R/W .1 x R/W
Set 1
.0 x R/W
Register addressing mode only Interrupt Level 7 (IRQ7) Enable Bit 0 1 Disable (mask) Enable (un-mask)
.6
Interrupt Level 6 (IRQ6) Enable Bit 0 1 Disable (mask) Enable (un-mask)
.5
Interrupt Level 5 (IRQ5) Enable Bit 0 1 Disable (mask) Enable (un-mask)
.4
Interrupt Level 4 (IRQ4) Enable Bit 0 1 Disable (mask) Enable (un-mask)
.3
Interrupt Level 3 (IRQ3) Enable Bit 0 1 Disable (mask) Enable (un-mask)
.2
Interrupt Level 2 (IRQ2) Enable Bit 0 1 Disable (mask) Enable (un-mask)
.1
Interrupt Level 1 (IRQ1) Enable Bit 0 1 Disable (mask) Enable (un-mask)
.0
Interrupt Level 0 (IRQ0) Enable Bit 0 1 Disable (mask) Enable (un-mask)
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
4-12
S3C84BB/F84BB
CONTROL REGISTERS
IPH -- Instruction Pointer (High Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
DAH
.2 x R/W .1 x R/W
Set 1
.0 x R/W
Register addressing mode only Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15-IP8). The lower byte of the IP address is located in the IPL register (DBH).
IPL -- Instruction Pointer (Low Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
DBH
.2 x R/W .1 x R/W
Set 1
.0 x R/W
Register addressing mode only Instruction Pointer Address (Low Byte) The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7-IP0). The upper byte of the IP address is located in the IPH register (DAH).
4-13
CONTROL REGISTERS
S3C84BB/F84BB
IPR -- Interrupt Priority Register
Bit Identifier RESET Value Read/Write Addressing Mode .7, .4, and .1 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
FFH
.2 x R/W
Set 1, Bank 0
.1 x R/W .0 x R/W
Register addressing mode only Priority Control Bits for Interrupt Groups A, B, and C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Group priority undefined B>C>A A>B>C B>A>C C>A>B C>B>A A>C>B Group priority undefined
.6
Interrupt Subgroup C Priority Control Bit 0 1 IRQ6 > IRQ7 IRQ7 > IRQ6
.5
Interrupt Group C Priority Control Bit 0 1 IRQ5 > (IRQ6, IRQ7) (IRQ6, IRQ7) > IRQ5
.3
Interrupt Subgroup B Priority Control Bit 0 1 IRQ3 > IRQ4 IRQ4 > IRQ3
.2
Interrupt Group B Priority Control Bit 0 1 IRQ2 > (IRQ3, IRQ4) (IRQ3, IRQ4) > IRQ2
.0
Interrupt Group A Priority Control Bit 0 1 IRQ0 > IRQ1 IRQ1 > IRQ0
4-14
S3C84BB/F84BB
CONTROL REGISTERS
IRQ -- Interrupt Request Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 0 R .6 0 R .5 0 R .4 0 R .3 0 R
DCH
.2 0 R .1 0 R
Set 1
.0 0 R
Register addressing mode only Level 7 (IRQ7) Request Pending Bit 0 1 Not pending Pending
.6
Level 6 (IRQ6) Request Pending Bit 0 1 Not pending Pending
.5
Level 5 (IRQ5) Request Pending Bit 0 1 Not pending Pending
.4
Level 4 (IRQ4) Request Pending Bit 0 1 Not pending Pending
.3
Level 3 (IRQ3) Request Pending Bit 0 1 Not pending Pending
.2
Level 2 (IRQ2) Request Pending Bit 0 1 Not pending Pending
.1
Level 1 (IRQ1) Request Pending Bit 0 1 Not pending Pending
.0
Level 0 (IRQ0) Request Pending Bit 0 1 Not pending Pending
4-15
CONTROL REGISTERS
S3C84BB/F84BB
P0CON -- Port 0 Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F0H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P0.7/P0.6/P0.5/P0.4 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative function mode (PGOUT<7:4>)
.5-.4
P0.3/P0.2 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative function mode (PGOUT<3:2>)
.3-.2
P0.1 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative function mode (PGOUT<1>)
.1-.0
P0.0 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative function mode (PGOUT<0>)
4-16
S3C84BB/F84BB
CONTROL REGISTERS
P1CON -- Port 1 Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F1H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P1.7/P1.6 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
.5-.4
P1.5/P1.4 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
.3-.2
P1.3/P1.2 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
.1-.0
P1.1/P1.0 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
4-17
CONTROL REGISTERS
S3C84BB/F84BB
P2CONH -- Port 2 Control Register (High Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F2H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P2.7/TAOUT 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode(TAOUT)
.5-.4
P2.6/TACAP 0 0 1 1 0 1 0 1 Input mode(TACAP) Input mode, pull-up(TACAP) Push-pull output Alternative output mode(Not used)
.3-.2
P2.5/TACK 0 0 1 1 0 1 0 1 Input mode(TACK) Input mode, pull-up(TACK) Push-pull output Alternative output mode(Not used)
.1-.0
P2.4/ TBPWM 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode(TBPWM)
4-18
S3C84BB/F84BB
CONTROL REGISTERS
P2CONL -- Port 2 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F3H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P2.3/DAOUT 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode (DAOUT)
.5-.4
P2.2/SCK 0 0 1 1 0 1 0 1 Input mode (SCK input) Input mode, pull-up (SCK input) Push-pull output Alternative output mode (SCK output)
.3-.2
P2.1/SI 0 0 1 1 0 1 0 1 Input mode(SI) Input mode, pull-up(SI) Push-pull output Alternative output mode(Not used)
.1-.0
P2.0/SO 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode (SO)
4-19
CONTROL REGISTERS
S3C84BB/F84BB
P3CONH -- Port 3 Control Register (High Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F4H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P3.7/TCOUT1 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode(TCOUT1)
.5-.4
P3.6/TCOUT0 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode(TCOUT0)
.3-.2
P3.5/ T1OUT1 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode(T1OUT1)
.1-.0
P3.4/ T1OUT0 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Alternative output mode(T1OUT0)
4-20
S3C84BB/F84BB
CONTROL REGISTERS
P3CONL -- Port 3 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F5H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P3.3/T1CAP1 0 0 1 0 1 x Input mode (T1CAP1) Input mode, pull-up (T1CAP1) Push-pull output
.5-.4
P3.2/ T1CAP0 0 0 1 0 1 x Input mode (T1CAP0) Input mode, pull-up (T1CAP0) Push-pull output
.3-.3
P3.1/T1CK1 0 0 1 0 1 x Input mode (T1CK1) Input mode, pull-up (T1CK1) Push-pull output
.1-.0
P3.0/T1CK0 0 0 1 0 1 x Input mode (T1CK0) Input mode, pull-up (T1CK0) Push-pull output
4-21
CONTROL REGISTERS
S3C84BB/F84BB
P4CONH -- Port 4 Control Register (High Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F6H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P4.7/INT7 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
.5-.4
P4.6/ INT6 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
.3-.2
P4.5/ INT5 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
.1-.0
P4.4/ INT4 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
4-22
S3C84BB/F84BB
CONTROL REGISTERS
P4CONL -- Port 4 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F7H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P4.3/INT3 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
.5-.4
P4.2/INT2 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
.3-.2
P4.1/INT1 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
.1-.0
P4.0/INT0 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
4-23
CONTROL REGISTERS
S3C84BB/F84BB
P4INT -- Port 4 Interrupt Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
FAH
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P4.7 External Interrupt (INT7) Enable Bit 0 1 Disable interrupt Enable interrupt
.6
P4.6 External Interrupt (INT6) Enable Bit 0 1 Disable interrupt Enable interrupt
.5
P4.5 External Interrupt (INT5) Enable Bit 0 1 Disable interrupt Enable interrupt
.4
P4.4 External Interrupt (INT4) Enable Bit 0 1 Disable interrupt Enable interrupt
.3
P4.3 External Interrupt (INT3) Enable Bit 0 1 Disable interrupt Enable interrupt
.2
P4.2 External Interrupt (INT2) Enable Bit 0 1 Disable interrupt Enable interrupt
.1
P4.1 External Interrupt (INT1) Enable Bit 0 1 Disable interrupt Enable interrupt
.0
P4.0 External Interrupt (INT0) Enable Bit 0 1 Disable interrupt Enable interrupt
4-24
S3C84BB/F84BB
CONTROL REGISTERS
P4INTPND -- Port 4 Interrupt Pending Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
FBH
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P4.7/INT7 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.6
P4.6/INT6 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.5
P4.5/INT5 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.4
P4.4/INT4 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.3
P4.3/INT3 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.2
P4.2/INT2 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.1
P4.1/INT1 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.0
P4.0/INT0 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
4-25
CONTROL REGISTERS
S3C84BB/F84BB
P5CONH -- Port 5 Control Register (High Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F8H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P5.7 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Open-drain mode
.5-.4
P5.6 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Open-drain mode
.3-.2
P5.5 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Open-drain mode
.1-.0
P5.4 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output Open-drain mode
4-26
S3C84BB/F84BB
CONTROL REGISTERS
P5CONL -- Port 5 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F9H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P5.3/RxD0 0 0 1 1 0 1 0 1 Input mode (RxD0 input) Input mode, pull-up mode (RxD0 input) Push-pull output Alternative output mode (RxD0 output)
.5-.4
P5.2/TxD0 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up mode Push-pull output Alternative output mode (TxD0 output)
.3-.2
P5.1/RxD1 0 0 1 1 0 1 0 1 Input mode (RxD1 input) Input mode, pull-up mode (RxD1 input) Push-pull output Alternative output mode (RxD1 output)
.1-.0
P5.0/TxD1 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up mode Push-pull output Alternative output mode (TxD1 output)
4-27
CONTROL REGISTERS
S3C84BB/F84BB
P7CON -- Port 7 Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F5H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only P7.7/ADC7 0 1 Input mode ADC input mode
.6
P7.6/ ADC6 0 1 Input mode ADC input mode
.5
P7.5/ ADC5 0 1 Input mode ADC input mode
.4
P7.4/ ADC4 0 1 Input mode ADC input mode
.3
P7.3/ ADC3 0 1 Input mode ADC input mode
.2
P7.2/ ADC2 0 1 Input mode ADC input mode
.1
P7.1/ ADC1 0 1 Input mode ADC input mode
.0
P7.0/ ADC0 0 1 Input mode ADC input mode
4-28
S3C84BB/F84BB
CONTROL REGISTERS
P8CONH -- Port 8 Control Register (High Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.4 - .3-.2 .7 1 -- .6 1 - .5 1 - .4 1 -.3 0 R/W
EDH
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only Not used for the S3C84BB/F84BB (must keep always 1) P8.5/ INT9 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
.1-.0
P8.4/ INT8 0 0 1 1 0 1 0 1 Input mode; falling edge interrupt Input mode; rising edge interrupt Input mode, pull-up; falling edge interrupt Push-pull output
4-29
CONTROL REGISTERS
S3C84BB/F84BB
P8CONL -- Port 8 Control Register (Low Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
EEH
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only P8.3 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
.5-.4
P8.2 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
.3-.2
P8.1 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
.1-.0
P8.0 0 0 1 0 1 x Input mode Input mode, pull-up Push-pull output
4-30
S3C84BB/F84BB
CONTROL REGISTERS
P8INTPND -- Port 8 Interrupt Pending Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .5 .7 1 - .6 1 - .5 0 R/W .4 0 R/W .3 1 -
EFH
.2 1 -
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only Not used for the S3C84BB/F84BB (must keep always 1) P8.5/INT9 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.4
P8.4/INT8 Interrupt Pending Bit 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.3-.2 .1
Not used for the S3C84BB/F84BB (must keep always 1) P8.5/INT9 Interrupt Enable 0 1 Disable interrupt Enable interrupt
.0
P8.4/INT8 Interrupt Enable 0 1 Disable interrupt Enable interrupt
4-31
CONTROL REGISTERS
S3C84BB/F84BB
PGCON --
Bit Identifier RESET Value Read/Write Addressing Mode .7-.4 .3
Pattern Generation Control Register
.7 - - .6 - - .5 - - .4 - - .3 0 R/W
FEH
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Not used for the S3C84BB/F84BB Software Trigger Start Bit 0 1 No effect Software trigger start (will be automatically cleared)
.2
PG Operation Disable/Enable Selection Bit 0 1 PG operation disable PG operation enable
.1-.0
PG Operation Trigger Mode Selection Bits 0 0 1 1 0 1 0 1 Timer A match siganal triggering Timer B underflow siganal triggering Timer 1(0) match siganal triggering Software triggering mode
4-32
S3C84BB/F84BB
CONTROL REGISTERS
PP -- Register Page Pointer
Bit Identifier RESET Value Read/Write Addressing Mode .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
DFH
.2 0 R/W .1 0 R/W
Set 1
.0 0 R/W
Register addressing mode only Destination Register Page Selection Bits 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Destination: page 0 Destination: page 1 Destination: page 2 Destination: page 3 Destination: page 4 Destination: page 5 Destination: page 6 Destination: page 7
.3-.0
Source Register Page Selection Bits 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Source: page 0 Source: page 1 Source: page 2 Source: page 3 Source: page 4 Source: page 5 Source: page 6 Source: page 7
NOTE: In the S3C84BB/F84BB microcontroller, the internal register file is configured as eight pages (Pages 0-7). The pages 0-1 are used for general-purpose register file, and page 2-7 is used for data register or general purpose registers.
4-33
CONTROL REGISTERS
S3C84BB/F84BB
RP0 -- Register Pointer 0
Bit Identifier RESET Value Read/Write Addressing Mode .7-.3 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 0 R/W
D6H
.2 - - .1 - -
Set 1
.0 - -
Register addressing only Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H-C7H.
.2-.0
Not used for the S3C84BB/F84BB
RP1 -- Register Pointer 1
Bit Identifier RESET Value Read/Write Addressing Mode .7-.3 .7 1 R/W .6 1 R/W .5 0 R/W .4 0 R/W .3 1 R/W
D7H
.2 - - .1 - -
Set 1
.0 - -
Register addressing only Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP1 points to address C8H in register set 1, selecting the 8-byte working register slice C8H-CFH.
.2-.0
Not used for the S3C84BB/F84BB
4-34
S3C84BB/F84BB
CONTROL REGISTERS
SIOCON -- SIO Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
E1H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only SIO Shift Clock Selection Bit 0 1 Internal clock (P.S clock) External clock (SCK)
.6
Data Direction Control Bit 0 1 MSB first mode LSB first mode
.5
SIO Mode Selection Bit 0 1 Receive only mode Transmit/receive mode
.4
Shift Start Edge Selection Bit 0 1 Tx at falling edges, Rx at rising edges Tx at rising edges, Rx at falling edges
.3
SIO Counter Clear and Shift Start Bit 0 1 No action Clear 3-bit counter and start shifting (Auto-clear bit)
.2
SIO Shift Operation Enable Bit 0 1 Disable shifter and clock counter Enable shifter and clock counter
.1
SIO Interrupt Enable Bit 0 1 Disable SIO interrupt Enable SIO interrupt
.0
SIO Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending condition (when write) Interrupt is pending
4-35
CONTROL REGISTERS
S3C84BB/F84BB
SIOPS -- SIO Prescaler Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F4H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Baud rate = Input clock (fxx)/[(SIOPS + 1) x2] or SCK input clock
4-36
S3C84BB/F84BB
CONTROL REGISTERS
SPH -- Stack Pointer (High Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
D8H
.2 x R/W .1 x R/W
Set 1
.0 x R/W
Register addressing mode only Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15-SP8). The lower byte of the stack pointer value is located in register SPL (D9H). The SP value is undefined following a reset.
SPL -- Stack Pointer (Low Byte)
Bit Identifier RESET Value Read/Write Addressing Mode .7-.0 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W
D9H
.2 x R/W .1 x R/W
Set 1
.0 x R/W
Register addressing mode only Stack Pointer Address (Low Byte) The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (SP7-SP0). The upper byte of the stack pointer value is located in register SPH (D8H). The SP value is undefined following a reset.
4-37
CONTROL REGISTERS
S3C84BB/F84BB
SYM -- System Mode Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .6 and .5 .4-.2 .7 0 R/W .6 - - .5 - - .4 x R/W .3 x R/W
DEH
.2 x R/W .1 0 R/W
Set 1
.0 0 R/W
Register addressing mode only Not used, But you must keep "0" Not used for S3C84BB/F84BB Fast Interrupt Level Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 IRQ0 IRQ1 IRG2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
.1
Fast Interrupt Enable Bit 0 1 Disable fast interrupt processing Enable fast interrupt processing
.0
Global Interrupt Enable Bit (note) 0 1 Disable global interrupt processing Enable global interrupt processing
NOTE: Following a reset, you enable global interrupt processing by executing an EI instruction (not by writing a "1" to SYM.0).
4-38
S3C84BB/F84BB
CONTROL REGISTERS
T1CON0 -- Timer 1(0) Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.5 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
EAH
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Timer 1 Input Clock Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/1024 fxx (Non-divide) fxx/256 External clock falling edge fxx/64 External clock rising edge fxx/8 Counter stop
.4-.3
Timer 1 Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode Capture mode (Capture on rising edge, OVF can occur) Capture mode (Capture on falling edge, OVF can occur) PWM mode
.2
Timer 1 Counter Enable Bit 0 1 No effect Clear the timer 1 counter (Auto-clear bit)
.1
Timer 1 Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer 1 Overflow Interrupt Enable 0 1 Disable overflow interrupt Enable overflow interrupt
4-39
CONTROL REGISTERS
S3C84BB/F84BB
T1CON1 -- Timer 1(1) Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.5 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
EBH
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Timer 1 Input Clock Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/1024 fxx (Non-divide) fxx/256 External clock falling edge fxx/64 External clock rising edge fxx/8 Counter stop
.4-.3
Timer 1 Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode Capture mode (Capture on rising edge, OVF can occur) Capture mode (Capture on falling edge, OVF can occur) PWM mode
.2
Timer 1 Counter Enable Bit 0 1 No effect Clear the timer 1 counter (Auto-clear bit)
.1
Timer 1 Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer 1 Overflow Interrupt Enable 0 1 Disable overflow interrupt Enable overflow interrupt
4-40
S3C84BB/F84BB
CONTROL REGISTER
TACON -- Timer A Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
EAH
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 - -
Register addressing mode only Timer A Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/1024 fxx/256 fxx/64 External clock (TACK)
.5-.4
Timer A Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode (TAOUT mode) Capture mode (capture on rising edge, counter running, OVF can occur) Capture mode (capture on falling edge, counter running, OVF can occur) PWM mode (OVF interrupt can occur)
.3
Timer A Counter Clear Bit 0 1 No effect Clear the timer A counter (After clearing, return to zero)
.2
Timer A Overflow Interrupt Enable Bit 0 1 Disable overflow interrupt Enable overflow interrupt
.1
Timer A Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Not used for the S3C84BB/F84BB
4-41
CONTROL REGISTERS
S3C84BB/F84BB
TBCON -- Timer B Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
D0H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only Timer B Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx fxx/2 fxx/4 fxx/8
.5-.4
Timer B Interrupt Time Selection Bits 0 0 1 1 0 1 0 1 Elapsed time for low data value Elapsed time for high data value Elapsed time for low and high data values Invalid setting
.3
Timer B Interrupt Enable Bit 0 1 Disable Interrupt Enable Interrupt
.2
Timer B Start/Stop Bit 0 1 Stop timer B Start timer B
.1
Timer B Mode Selection Bit 0 1 One-shot mode Repeating mode
.0
Timer B Output flip-flop Control Bit 0 1 T-FF is low T-FF is high
NOTE: fxx is selected clock for system.
4-42
S3C84BB/F84BB
CONTROL REGISTER
TCCON0 -- Timer C(0) Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .6-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F2H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Not used for the S3C84BB/F84BB (must keep always 0) Timer C 3-bits Prescaler Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Non devided Divided by 2 Divided by 3 Divided by 4 Divided by 5 Divided by 6 Divided by 7 Divided by 8
.3
Timer C Counter Clear Bit 0 1 No effect Clear the timer C(0) counter (Auto-clear bit)
.2
Timer C Mode Selection Bit 0 1 fxx/1 & PWM mode fxx/64 & interval mode
.1
Timer C Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer C Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
4-43
CONTROL REGISTERS
S3C84BB/F84BB
TCCON1 -- Timer C(1) Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7 .6-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
F3H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Not used for the S3C84BB/F84BB (must keep always 0) Timer C 3-bits Prescaler Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Non devided Divided by 2 Divided by 3 Divided by 4 Divided by 5 Divided by 6 Divided by 7 Divided by 8
.3
Timer C Counter Clear Bit 0 1 No effect Clear the timer C(1) counter (Auto-clear bit)
.2
Timer C Mode Selection Bit 0 1 fxx/1 & PWM mode fxx/64 & interval mode
.1
Timer C Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt
.0
Timer C Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
4-44
S3C84BB/F84BB
CONTROL REGISTER
TINTPND -- Timer A,1 Interrupt Pending Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .5 .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W
E9H
.2 0 R/W
Set 1, Bank 0
.1 0 R/W .0 0 R/W
Register addressing mode only Not used for the S3C84BB/F84BB Timer 1(1) Overflow Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
.4
Timer 1(1) Match/Capture Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
.3
Timer 1(0) Overflow Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
.2
Timer 1(0) Match/Capture Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
.1
Timer A Overflow Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
.0
Timer A Match/Capture Interrupt Pending Bit 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending
4-45
CONTROL REGISTERS
S3C84BB/F84BB
UARTCON0 -- UART0 Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
E3H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Operating mode and baud rate selection bits 0 0
1
0 1
0
Mode 0: SIO mode [fxx/(16 x (BRDATA0 + 1))] Mode 1: 8-bit UART [fxx/(16 x (BRDATA0 + 1))] Mode 2: 9-bit UART [fxx/16] Mode 3: 9-bit UART [fxx/(16 x (BRDATA0 + 1))]
1 .5
1
Multiprocessor communication(1) enable bit (for modes 2 and 3 only) 0 1 Disable Enable
.4
Serial data receive enable bit 0 1 Disable Enable
.3
Location of the 9th data bit to be transmitted in UART mode 2 or 3 ("0" or "1") Location of the 9th data bit that was received in UART mode 2 or 3 ("0" or "1") Receive interrupt enable bit 0 1 Disable Receive interrupt Enable Receive interrupt
.2 .1
.0
Transmit interrupt enable bit 0 1 Disable Transmit interrupt Enable Transmit Interrupt
NOTES: 1. In mode 2 or 3, if the MCE (UARTCON.5) bit is set to "1", then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if MCE = "1", then the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the MCE(UARTCON.5) bit should be "0". 2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
4-46
S3C84BB/F84BB
CONTROL REGISTER
UARTCON1 -- UART1 Control Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W
FBH
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Operating mode and baud rate selection bits 0 0
1
0 1
0
Mode 0: SIO mode [fxx/(16 x (BRDATA1 + 1))] Mode 1: 8-bit UART [fxx/(16 x (BRDATA1 + 1))] Mode 2: 9-bit UART [fxx/16] Mode 3: 9-bit UART [fxx/(16 x (BRDATA1 + 1))]
1 .5
1
Multiprocessor communication(1) enable bit (for modes 2 and 3 only) 0 1 Disable Enable
.4
Serial data receive enable bit 0 1 Disable Enable
.3
Location of the 9th data bit to be transmitted in UART mode 2 or 3 ("0" or "1") Location of the 9th data bit that was received in UART mode 2 or 3 ("0" or "1") Receive interrupt enable bit 0 1 Disable Receive interrupt Enable Receive interrupt
.2 .1
.0
Transmit interrupt enable bit 0 1 Disable Transmit interrupt Enable Transmit Interrupt
NOTES: 1. In mode 2 or 3, if the MCE (UARTCON.5) bit is set to "1", then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if MCE = "1", then the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the MCE(UARTCON.5) bit should be "0". 2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
4-47
CONTROL REGISTERS
S3C84BB/F84BB
UARTPND -- UART0,1 Pending Register
Bit Identifier RESET Value Read/Write Addressing Mode .7-.4 .3 .7 - - .6 - - .5 - - .4 - - .3 0 R/W
E5H
.2 0 R/W
Set 1, Bank 1
.1 0 R/W .0 0 R/W
Register addressing mode only Not used for S3C84BB/F84BB UART1 receive interrupt pending flag 0 0 1 Not pending Clear pending bit (when write) Interrupt pending
.2
UART1 transmit interrupt pending flag 0 0 1 Not pending Clear pending bit (when write) Interrupt pending
.1
UART0 receive interrupt pending flag 0 0 1 Not pending Clear pending bit (when write) Interrupt pending
.0
UART0 transmit interrupt pending flag 0 0 1 Not pending Clear pending bit (when write) Interrupt pending
NOTES: 1. In order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. 2. To avoid programming errors, we recommend using load instruction (except for LDB), when manipulating UARTPND values.
4-48
S3C84BB/F84BB
INTERRUPT STRUCTURE
INTERRUPT STRUCTURE
OVERVIEW
The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources. Levels Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0-IRQ7, also called level 0-level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3C84BB/F84BB interrupt structure recognizes eight interrupt levels. The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels. Vectors Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector priorities are set in hardware. S3C84BB/F84BB uses twenty four vectors. Sources A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each vector can have several interrupt sources. In the S3C84BB/F84BB interrupt structure, there are twenty four possible interrupt sources. When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.
5-1
INTERRUPT STRUCTURE
S3C84BB/F84BB
INTERRUPT TYPES The three components of the S3C8 interrupt structure described before -- levels, vectors, and sources -- are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1): Type 1: Type 2: Type 3: One level (IRQn) + one vector (V1) + one source (S1) One level (IRQn) + one vector (V1) + multiple sources (S1 - Sn) One level (IRQn) + multiple vectors (V1 - Vn) + multiple sources (S1 - Sn , Sn+1 - Sn+m)
In the S3C84BB/F84BB microcontroller, two interrupt types are implemented.
Levels Type 1: IRQn
Vectors V1
Sources S1 S1
Type 2:
IRQn
V1
S2 S3 Sn
V1 Type 3: IRQn V2 V3 Vn
S1 S2 S3 Sn Sn + 1
NOTES: 1. The number of Sn and Vn value is expandable. 2. In the S3C84BB/F84BB implementation, interrupt types 1 and 3 are used.
Sn + 2 Sn + m
Figure 5-1. S3C8-Series Interrupt Types
5-2
S3C84BB/F84BB
INTERRUPT STRUCTURE
S3C84BB/F84BB INTERRUPT STRUCTURE The S3C84BB/F84BB microcontroller supports twenty four interrupt sources. All twenty four of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware). When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.
5-3
INTERRUPT STRUCTURE
S3C84BB/F84BB
Levels
Vectors B8H
Sources Timer A match/capture Timer A overflow Timer B underflow Timer C(0) match/overflow Timer C(1) match/overflow Timer 1(0) match/capture Timer 1(0) overflow Timer 1(1) match/capture Timer 1(1) overflow SIO receive/transmit P8.4 external interrupt P8.5 external interrupt P4.0 external interrupt P4.1 external interrupt P4.2 external interrupt P4.3 external interrupt P4.4 external interrupt P4.5 external interrupt P4.6 external interrupt P4.7 external interrupt UART0 data receive UART0 data transmit UART1 data receive UART1 data transmit
Reset(Clear) H/W , S/W H/W , S/W H/W H/W , S/W H/W , S/W H/W , S/W H/W , S/W H/W , S/W H/W , S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W S/W
IRQ0 BAH IRQ1 IRQ2 BEH C0H IRQ3 C2H C4H C6H IRQ4 IRQ5 CEH IRQ6 E0H E2H E4H E6H E8H EAH ECH EEH IRQ7 F0H F2H F4H F6H CAH CCH C8H BCH
NOTES: 1. W ithin a given interrupt level, the lower vector address has high priority. For example, B8H has higher priority than BAH within the level IRQ0 the priorities within each level are set at the factory. 2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting.
Figure 5-2. S3C84BB/F84BB Interrupt Structure
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INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C84BB/F84BB interrupt structure are stored in the vector address area of the internal 64-Kbyte ROM, 0H-FFFFH (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses). The program reset address in the ROM is 0100H.
(Decimal) 65,535
(HEX) FFFFH
~ ~
64-Kbyte Memory Area
~ ~
255 Interrupt Vector Area 0
0100H FFH
RESET Address
00H
Figure 5-3. ROM Vector Address Area
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Table 5-1. Interrupt Vectors Vector Address Decimal Value 256 246 244 242 240 238 236 234 232 230 228 226 224 206 204 202 198 196 194 192 190 188 200 186 184 Hex Value 100H F6H F4H F2H F0H EEH ECH EAH E8H E6H E4H E2H E0H CEH CCH CAH C6H C4H C2H C0H BEH BCH C8H BAH B8H Interrupt Source Basic timer(WDT) overflow UART1 transmit UART1 receive UART0 transmit UART0 receive P4.7 external interrupt P4.6 external interrupt P4.5 external interrupt P4.4 external interrupt P4.3 external interrupt P4.2 external interrupt P4.1 external interrupt P4.0 external interrupt P8.5 external interrupt P8.4 external interrupt SIO receive/transmit Timer 1(1) overflow Timer 1(1) match/capture Timer 1(0) overflow Timer 1(0) match/capture Timer C(1) match/overflow Timer C(0) match/overflow Timer B underflow Timer A overflow Timer A match/capture IRQ1 IRQ0 IRQ2 IRQ4 IRQ3 IRQ5 IRQ6 Request Interrupt Level RESETB IRQ7 Priority in Level 3 2 1 0 7 6 5 4 3 2 1 0 1 0 3 2 1 0 1 0 1 0 Reset/Clear H/W S/W
NOTES: 1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on. 2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. The priorities within a given level are fixed in hardware.
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ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure. During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: -- The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels. -- The interrupt priority register, IPR, controls the relative priorities of interrupt levels. -- The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). -- The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented).
Table 5-2. Interrupt Control Register Overview Control Register Interrupt mask register Interrupt priority register ID IMR IPR R/W R/W R/W Function Description Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0-IRQ7. Controls the relative processing priorities of the interrupt levels. The seven levels of S3C84BB/F84BB are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7. This register contains a request pending bit for each interrupt level. This register enables/disables fast interrupt processing, dynamic global interrupt processing, and external interface control (An external memory interface is not implemented in the S3C84BB/F84BB microcontroller).
Interrupt request register System mode register
IRQ SYM
R R/W
NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.
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INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: -- Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0) -- Interrupt level enable/disable settings (IMR register) -- Interrupt level priority settings (IPR register) -- Interrupt source enable/disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information.
EI RESET IRQ0-IRQ7, Interrupts
S R
Q
Interrupt Request Register (Read-only)
Polling Cycle
Interrupt Priority Register
Vector Interrupt Cycle
Interrupt Mask Register
Global Interrupt Control (EI, DI or SYM.0 manipulation)
Figure 5-4. Interrupt Function Diagram
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PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers Interrupt Source Timer A overflow Timer A match/capture Interrupt Level IRQ0 Register(s) TINTPND TACON TADATA TACNT Timer B underflow Timer C(0) match/overflow Timer C(1) match/overflow IRQ1 IRQ2 TBCON TBDATAH, TBDATAL TCCON0 TCCON1 TCDATA0 TCDATA1 Timer1(0) match/capture Timer1(0) overflow Timer1(1)match/capture Timer1(1)overflow SIO receive/transmit P8.5 external interrupt P8.4 external interrupt P4.7 external interrupt P4.6 external interrupt P4.5 external interrupt P4.4 external interrupt P4.3 external interrupt P4.2 external interrupt P4.1 external interrupt P4.0 external interrupt UART0 receive/transmit UART1 receive/transmit IRQ7 UARTCON0 UARTCON1 UDATA0, UDATA1 UARTPND E3H, bank 1 FBH, bank 1 E2H, FAH, bank 1 E5H, bank 1 IRQ6 IRQ4 IRQ5 IRQ3 T1DATAH0,T1DATAL0 T1DATAH1,T1DATAL1 T1CON0, T1CON1 T1CNTH0, T1CNTL0 T1CNTH1, T1CNTL1 SIOCON, SIODATA P8CONH,P8CONL P8INTPND P4CONH P4CONL P4INT P4INTPND Location(s) in Set 1 E9H, bank 0 EAH, bank 0 EBH, bank 0 ECH, bank 0 D0H, bank 0 D1H, D2H, bank 0 F2H, bank 1 F3H, bank 1 F0H, bank 1 F1H, bank 1 E6H,E7H, bank 1 E8H,E9H, bank 1 EAH,EBH, bank1 ECH, EDH, bank1 EEH, EFH, bank1 E1H,E0H, bank1 EDH,EEH, bank0 EFH, bank0 F6H, bank 0 F7H, bank 0 FAH, bank 0 FBH, bank 0
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SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing (see Figure 5-5). A reset clears SYM.0 to "0". The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose.
System Mode Register (SYM) DEH, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used for the S3C84BB/F84BB Fast interrupt level selection bits: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Global interrupt enable bit: 0 = Disable all interrupts processing 1 = Enable all interrupts processing Fast interrupt enable bit: 0 = Disable fast interrupts processing 1 = Enable fast interrupts processing
Figure 5-5. System Mode Register (SYM)
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INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit to "1", interrupt processing for the level is enabled (not masked). The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode.
Interrupt Mask Register (IMR) DDH ,Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
IRQ1 IRQ0 IRQ3 IRQ2 IRQ5 IRQ4 IRQ7 IRQ6 Interrupt level # enable bit 0 = Disable IRQ# interrupt 1 = Enable IRQ# interrupt
Figure 5-6. Interrupt Mask Register (IMR)
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INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This priority is fixed in hardware). To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7): Group A Group B Group C IRQ0, IRQ1 IRQ2, IRQ3, IRQ4 IRQ5, IRQ6, IRQ7
IPR Group A
IPR Group B
IPR Group C
A1
A2
B1 B21
B2 B22 IRQ4
C1 C21 IRQ5 IRQ6
C2 C22 IRQ7
IRQ0
IRQ1
IRQ2 IRQ3
Figure 5-7. Interrupt Request Priority Groups As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would select the relationship C > B > A. The functions of the other IPR bit settings are as follows: -- IPR.5 controls the relative priorities of group C interrupts. -- Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C. -- IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
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Interrupt Priority Register (IPR) FFH ,Set 1, Bank 0, R/W MSB Group priority: D7 D4 D1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 = = = = = = = = Undefined B>C>A A > B >C B>A>C C>A>B C>B>A A>C>B Undefined .7 .6 .5 .4 .3 .2 .1 .0 LSB Group A 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Group B 0 = IRQ2 > (IRQ3, IRQ4) 1 = (IRQ3, IRQ4) > IRQ2 Subgroup B 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Group C 0 = IRQ5 > (IRQ6, IRQ7) 1 = (IRQ6, IRQ7) > IRQ5 Subgroup C 0 = IRQ6 > IRQ7 1 = IRQ7 > IRQ6
Figure 5-8. Interrupt Priority Register (IPR)
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INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A "1" indicates that an interrupt request has been generated for that level. IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to "0". You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled.
Interrupt Request Register (IRQ) DCH ,Set 1, R MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
IRQ1 IRQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2
Interrupt level # request pending bit 0 = IRQ# interrupt is not pending 1 = IRQ# interrupt is pending
Figure 5-9. Interrupt Request Register (IRQ)
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INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3C84BB/F84BB interrupt structure, the timer B underflow interrupt (IRQ1) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source's mode or control register. In the S3C84BB/F84BB interrupt structure, pending conditions for IRQ4, IRQ5, IRQ6, and IRQ7 must be cleared in the interrupt service routine.
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INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the source's interrupt level. 4. The CPU generates an interrupt acknowledge signal. 5. Interrupt logic determines the interrupt's vector address. 6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. The CPU continues polling for interrupt requests.
INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced, the following conditions must be met: -- Interrupt processing must be globally enabled (EI, SYM.0 = "1") -- The interrupt level must be enabled (IMR register) -- The interrupt level must have the highest priority if more than one level is currently requesting service -- The interrupt must be enabled at the interrupt's source (peripheral control register) When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts. 2. Save the program counter (PC) and status flags to the system stack. 3. Branch to the interrupt vector to fetch the address of the service routine. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.
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GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H-FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. 2. Push the program counter's high-byte value to the stack. 3. Push the FLAG register values to the stack. 4. Fetch the service routine's high-byte address from the vector location. 5. Fetch the service routine's low-byte address from the vector location. 6. Branch to the service routine specified by the concatenated 16-bit vector address. NOTE A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H-FFH.
NESTING OF VECTORED INTERRUPTS It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps: 1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR). 2. Load the IMR register with a new mask value that enables only the higher priority interrupt. 3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR). 5. Execute an IRET. Depending on the application, you may be able to simplify the procedure above to some extent.
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NOTES
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INSTRUCTION SET
OVERVIEW
The instruction set is specifically designed to support large register files that are typical of most S3C8-series microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: -- A full complement of 8-bit arithmetic and logic operations, including multiply and divide -- No special I/O instructions (I/O control/data registers are mapped directly into the register file) -- Decimal adjustment included in binary-coded decimal (BCD) operations -- 16-bit (word) data can be incremented and decremented -- Flexible instructions for bit addressing, rotate, and shift operations
DATA TYPES The CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data, 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Chapter 2, "Address Spaces." ADDRESSING MODES There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to Chapter 3, "Addressing Modes."
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Table 6-1. Instruction Group Summary Mnemonic Operands Instruction
Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst dst,src dst,src src dst,src dst,src Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre-decrement Load program memory with pre-decrement Load external data memory with pre-increment Load program memory with pre-increment Load word Pop from stack Pop user stack (decrementing) Pop user stack (incrementing) Push to stack Push user stack (decrementing) Push user stack (incrementing)
NOTE: LDE, LDED, LDEI, LDEPP, and LDEPI instructions can be used to read/write the data from the 64-Kbyte data memory.
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Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Arithmetic Instructions ADC ADD CP DA DEC DECW DIV INC INCW MULT SBC SUB dst,src dst,src dst,src dst dst dst dst,src dst dst dst,src dst,src dst,src Add with carry Add Compare Decimal adjust Decrement Decrement word Divide Increment Increment word Multiply Subtract with carry Subtract
Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR
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Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Program Control Instructions BTJRF BTJRT CALL CPIJE CPIJNE DJNZ ENTER EXIT IRET JP JP JR NEXT RET WFI cc,dst dst cc,dst dst,src dst,src dst dst,src dst,src r,dst Bit test and jump relative on false Bit test and jump relative on true Call procedure Compare, increment and jump on equal Compare, increment and jump on non-equal Decrement register and jump on non-zero Enter Exit Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Next Return Wait for interrupt
Bit Manipulation Instructions BAND BCP BITC BITR BITS BOR BXOR TCM TM dst,src dst,src dst dst dst dst,src dst,src dst,src dst,src Bit AND Bit compare Bit complement Bit reset Bit set Bit OR Bit XOR Test complement under mask Test under mask
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Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction
Rotate and Shift Instructions RL RLC RR RRC SRA SWAP dst dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles
CPU Control Instructions CCF DI EI IDLE NOP RCF SB0 SB1 SCF SRP SRP0 SRP1 STOP src src src Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode
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FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits which describe the current status of CPU operations. Four of these bits, FLAGS.7-FLAGS.4, can be tested and used with conditional jump instructions. Two other flag bits, FLAGS.3 and FLAGS.2, are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether register bank 0 or bank 1 is currently being addressed. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then two write will simultaneously occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS) D5H ,Set 1, R/W MSB Carry flag (C) Zero flag (Z) Sign flag (S) Overflow flag (V) .7 .6 .5 .4 .3 .2 .1 .0 LSB Bank address status flag (BA) Fast interrupt status flag (FS) Half-carry flag (H) Decimal adjust flag (D)
Figure 6-1. System Flags Register (FLAGS)
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FLAG DESCRIPTIONS
C
Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations have been performed, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.
Z
Zero Flag (FLAGS.6) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. In operations that test register bits, and in shift and rotate operations, the Z flag is set to "1" if the result is logic zero.
S
Sign Flag (FLAGS.5) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number.
V
Overflow Flag (FLAGS.4) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is cleared to "0" after a logic operation has been performed.
D
Decimal Adjust Flag (FLAGS.3) The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and it cannot be addressed as a test condition.
H
Half-Carry Flag (FLAGS.2) The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is normally not accessed directly by a program.
FIS
Fast Interrupt Status Flag (FLAGS.1) The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed.
BA
Bank Address Flag (FLAGS.0) The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when the SB0 instruction is executed and is set to "1" (select bank 1) when the SB1 instruction is executed.
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INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S V D H 0 1 * - x Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Description
Table 6-3. Instruction Set Symbols Symbol dst src @ PC IP FLAGS RP # H D B opc Source operand Indirect register address prefix Program counter Instruction pointer Flags register (D5H) Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode Description Destination operand
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Table 6-4. Instruction Notation Conventions Notation cc r rb r0 rr R Rb RR IA Ir IR Irr IRR X XS XL DA RA IM IML Condition code Working register only Bit (b) of working register Bit 0 (LSB) of working register Working register pair Register or working register Bit "b" of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode Indexed (long offset) addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate (long) addressing mode Description Rn (n = 0-15) Rn.b (n = 0-15, b = 0-7) Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg.b (reg = 0-255, b = 0-7) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) addr (addr = 0-254, even number only) @Rn (n = 0-15) @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg[Rn] (reg = 0-255, n = 0-15) #addr[RRp] (addr = range -128 to +127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-65535, where p = 2, ..., 14) addr (addr = range 0-65535) addr (addr = a number from +127 to -128 that is an offset relative to the address of the next instruction) #data (data = 0-255) #data (data = 0-65535) Actual Operand Range See list of condition codes in Table 6-6.
Indirect register or indirect working register @Rn or @reg (reg = 0-255, n = 0-15)
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Table 6-5. OPCODE Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F 0 DEC R1 RLC R1 INC R1 JP IRR1 DA R1 POP R1 COM R1 PUSH R2 DECW RR1 RL R1 INCW RR1 CLR R1 RRC R1 SRA R1 RR R1 SWAP R1 1 DEC IR1 RLC IR1 INC IR1 SRP/0/1 IM DA IR1 POP IR1 COM IR1 PUSH IR2 DECW IR1 RL IR1 INCW IR1 CLR IR1 RRC IR1 SRA IR1 RR IR1 SWAP IR1 2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2 AND r1,r2 TCM r1,r2 TM r1,r2 PUSHUD IR1,R2 POPUD IR2,R1 CP r1,r2 XOR r1,r2 CPIJE Ir,r2,RA CPIJNE Irr,r2,RA LDCD r1,Irr2 LDCPD r2,Irr1 3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2 PUSHUI IR1,R2 POPUI IR2,R1 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LDCPI r2,Irr1 4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1 MULT R2,RR1 DIV R2,RR1 CP R2,R1 XOR R2,R1 LDW RR2,RR1 CALL IA1 LD R2,R1 CALL IRR1 LD R2,IR1 LD IR2,R1 5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1 MULT IR2,RR1 DIV IR2,RR1 CP IR2,R1 XOR IR2,R1 LDW IR2,RR1 6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM MULT IM,RR1 DIV IM,RR1 CP R1,IM XOR R1,IM LDW RR1,IML LD IR1,IM LD R1,IM CALL DA1 7 BOR r0-Rb BCP r1.b, R2 BXOR r0-Rb BTJR r2.b, RA LDB r0-Rb BITC r1.b BAND r0-Rb BIT r1.b LD r1, x, r2 LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs
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Table 6-5. OPCODE Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC r1 8 LD r1,R2 9 LD r2,R1 A DJNZ r1,RA B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F NEXT ENTER EXIT WFI SB0 SB1 IDLE

STOP DI EI RET IRET RCF

SCF CCF NOP
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CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 (1) 1111 (1) 0110 1110 1101 0101 0100 1100 0110 (1) 1110 (1) 1001 0001 1010 0010 1111 0111 1011 0011
(1) (1) (1) (1)
Mnemonic F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal
Description Always false C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0
Flags Set - -
Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal
(S XOR V) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1
NOTES: 1. It indicate condition codes which are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used. Following a CP instruction, you would probably want to use the instruction EQ. 2. For operations using unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
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INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction in the S3C8-series instruction set. Information is arranged in a consistent format for improved readability and for quick reference. The following information is included in each instruction description: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Shorthand notation of the instruction's operation -- Textual description of the instruction's effect -- Flag settings that may be affected by the instruction -- Detailed description of the instruction's format, execution time, and addressing mode(s) -- Programming example(s) explaining how to use the instruction
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ADC -- Add with Carry
ADC Operation: dst,src dst dst + src + c The source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple-precision arithmetic, this instruction lets the carry value from the addition of low-order operands be carried into the addition of high-order operands. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 Opcode (Hex) 12 13 14 15 opc Examples: dst src 3 6 16 Addr Mode dst src r r R R R r lr R IR IM
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H
In the first example, the destination register R1 contains the value 10H, the carry flag is set to "1" and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in the register R1.
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ADD -- Add
ADD Operation: dst,src dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 Opcode (Hex) 02 03 04 05 opc Examples: dst src 3 6 06 Addr Mode dst src r r R R R r lr R IR IM
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H
In the first example, the destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in the register R1.
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AND -- Logical AND
AND Operation: dst,src dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation causes a "1" bit to be stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 Opcode (Hex) 52 53 54 55 opc dst src 3 6 56 Addr Mode dst src r r R R R r lr R IR IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H
In the first example, the destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in the register R1.
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BAND -- Bit AND
BAND BAND Operation: dst,src.b dst.b,src dst(0) dst(0) AND src(b) or dst(b) dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or the source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) 67 67 Addr Mode dst src r0 Rb Rb r0
opc opc
dst | b | 0
src dst
3 3
6 6
src | b | 1
NOTE: In the second byte of the 3-byte instruction formats, the destination (or the source) address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H and register 01H = 05H: BAND BAND R1,01H.1 01H.1,R1 R1 = 06H, register 01H = 05H Register 01H = 05H, R1 = 07H
In the first example, the source register 01H contains the value 05H (00000101B) and the destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of the register R1 (destination), leaving the value 06H (00000110B) in the register R1.
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BCP -- Bit Compare
BCP Operation: dst,src.b dst(0) - src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Unaffected. Z: Set if the two bits are the same; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes opc
dst | b | 0
Cycles 6
Opcode (Hex) 17
Addr Mode dst src r0 Rb
src
3
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "0" is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H and register 01H = 01H: BCP R1,01H.1 R1 = 07H, register 01H = 01H
If the destination working register R1 contains the value 07H (00000111B) and the source register 01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).
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BITC -- Bit Complement
BITC Operation: dst.b dst(b) NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bit in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes opc
dst | b | 0
Cycles 4
Opcode (Hex) 57
Addr Mode dst rb
2
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H BITC R1.1 R1 = 05H
If the working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in the register R1. Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared.
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BITR -- Bit Reset
BITR Operation: dst.b dst(b) 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination. Flags: Format: Bytes opc
dst | b | 0
No flags are affected.
Cycles 4
Opcode (Hex) 77
Addr Mode dst rb
2
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "0" is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H: BITR R1.1 R1 = 05H
If the value of the working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B).
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BITS -- Bit Set
BITS Operation: dst.b dst(b) 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination. Flags: Format: Bytes opc
dst | b | 1
No flags are affected.
Cycles 4
Opcode (Hex) 77
Addr Mode dst rb
2
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H: BITS R1.3 R1 = 0FH
If the working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B).
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BOR -- Bit OR
BOR BOR Operation: dst,src.b dst.b,src dst(0) dst(0) OR src(b) or dst(b) dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes opc opc
dst | b | 0
Cycles 6 6
Opcode (Hex) 07 07
Addr Mode dst src r0 Rb Rb r0
src dst
3 3
src | b | 1
NOTE: In the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the LSB address value is one bit.
Examples:
Given: R1 = 07H and register 01H = 03H: BOR BOR R1, 01H.1 01H.2, R1 R1 = 07H, register 01H = 03H Register 01H = 07H, R1 = 07H
In the first example, the destination working register R1 contains the value 07H (00000111B) and the source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of the register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in the working register R1. In the second example, the destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically ORs bit two of the register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in the register 01H.
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BTJRF -- Bit Test, Jump Relative on False
BTJRF Operation: dst,src.b If src(b) is a "0", then PC PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter. Otherwise, the instruction following the BTJRF instruction is executed. Flags: Format: Bytes
(note)
No flags are affected.
Cycles 10
Opcode (Hex) 37
Addr Mode dst src RA rb
opc
src | b | 0
dst
3
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H: BTJRF SKIP,R1.3 PC jumps to SKIP location
If the working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP (Remember that the memory location must be within the allowed range of + 127 to - 128).
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BTJRT -- Bit Test, Jump Relative on True
BTJRT Operation: dst,src.b If src(b) is a "1", then PC PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC. Otherwise, the instruction following the BTJRT instruction is executed. Flags: Format: Bytes
(note)
No flags are affected.
Cycles 10
Opcode (Hex) 37
Addr Mode dst src RA rb
opc
src | b | 1
dst
3
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H: BTJRT SKIP,R1.1
If the working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of + 127 to - 128.
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BXOR -- Bit XOR
BXOR BXOR Operation: dst,src.b dst.b,src dst(0) dst(0) XOR src(b) or dst(b) dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or the source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes opc opc
dst | b | 0
Cycles 6 6
Opcode (Hex) 27 27
Addr Mode dst src r0 Rb Rb r0
src dst
3 3
src | b | 1
NOTE: In the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B): BXOR BXOR R1,01H.1 01H.2,R1 R1 = 06H, register 01H = 03H Register 01H = 07H, R1 = 07H
In the first example, the destination working register R1 has the value 07H (00000111B) and the source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusiveORs bit one of the register 01H (the source) with bit zero of R1 (the destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of the source register 01H is unaffected.
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CALL -- Call Procedure
CALL Operation: dst SP SP-1 @SP PCL SP SP-1 @SP PCH PC dst The contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: Format: Bytes opc opc opc Examples: dst dst dst 3 2 2 Cycles 14 12 14 Opcode (Hex) F6 F4 D4 Addr Mode dst DA IRR IA No flags are affected.
Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H: CALL 3521H SP = 0000H (Memory locations 0000H = 1AH, 0001H = 4AH, where, 4AH is the address that follows the instruction.) SP = 0000H (0000H = 1AH, 0001H = 49H) SP = 0000H (0000H = 1AH, 0001H = 49H)
CALL CALL
@RR0 #40H
In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to the memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and the stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. Assuming that the contents of the program counter and the stack pointer are the same as in the first example, if the program address 0040H contains 35H and the program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example.
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CCF -- Complement Carry Flag
CCF Operation: C NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero. If C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Format: Bytes opc Example: Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one. 1 Cycles 4 Opcode (Hex) EF
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CLR -- Clear
CLR Operation: dst dst "0" The destination location is cleared to "0". Flags: Format: Bytes opc dst 2 Cycles 4 4 Examples: Opcode (Hex) B0 B1 Addr Mode dst R IR No flags are affected.
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H Register 00H = 00H Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.
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COM -- Complement
COM Operation: dst dst NOT dst The contents of the destination location are complemented (one's complement). All "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Examples: Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH Opcode (Hex) 60 61 Addr Mode dst R IR
In the first example, the destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and logic zeros to logic ones, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of the destination register 07H (11110001B), leaving the new value 0EH (00001110B).
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CP -- Compare
CP Operation: dst,src dst-src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc Examples: dst src 3 6 Opcode (Hex) A2 A3 A4 A5 A6 Addr Mode dst src r r R R R r lr R IR IM
1. Given: R1 = 02H and R2 = 03H: CP R1,R2 Set the C and S flags
The destination working register R1 contains the value 02H and the source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, the C and the S flag values are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC SKIP R1,R2 UGE,SKIP R1 LD R3,R1
In this example, the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in the working register R3.
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CPIJE -- Compare, Increment, and Jump on Equal
CPIJE Operation: dst,src,RA If dst-src = "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed. Flags: Format: Bytes opc src dst RA 3 Cycles 12 Opcode (Hex) C2 Addr Mode dst src r Ir No flags are affected.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 02H: CPIJE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location
In this example, the working register R1 contains the value 02H, the working register R2 the value 03H, and the register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H. Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of + 127 to - 128.
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CPIJNE -- Compare, Increment, and Jump on Non-Equal
CPIJNE Operation: dst,src,RA If dst-src "0", PC PC + RA Ir Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction. Flags: Format: Bytes opc src dst RA 3 Cycles 12 Opcode (Hex) D2 Addr Mode dst src r Ir No flags are affected.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 04H: CPIJNE R1,@R2,SKIP R2 = 04H, PC jumps to SKIP location
The working register R1 contains the value 02H, the working register R2 (the source pointer) the value 03H, and the general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H (00000100B) from 02H (00000010B). Because the result of the comparison is nonequal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of + 127 to - 128.
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DA -- Decimal Adjust
DA Operation: dst dst DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed (The operation is undefined if the destination operand is not the result of a valid addition or subtraction of BCD digits): Instruction Carry Before DA 0 0 0 ADD ADC 0 0 0 1 1 1 0 SUB SBC 0 1 1 Flags: Bits 4-7 Value (Hex) 0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3 0-9 0-8 7-F 6-F H Flag Before DA 0 0 1 0 0 1 0 0 1 0 1 0 1 Bits 0-3 Value (Hex) 0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 6-F 0-9 6-F Number Added to Byte 00 06 06 60 66 66 60 66 66 00 = - 00 FA = - 06 A0 = - 60 9A = - 66 Carry After DA 0 0 0 1 1 1 1 1 1 0 0 1 1
C: Set if there was a carry from the most significant bit; cleared otherwise (see table). Z: Set if result is "0"; cleared otherwise. S: Set if result bit 7 is set; cleared otherwise. V: Undefined. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 40 41 Addr Mode dst R IR
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DA -- Decimal Adjust
DA Example: (Continued) Given: The working register R0 contains the value 15 (BCD), the working register R1 contains 27 (BCD), and the address 27H contains 46 (BCD): ADD DA R1,R0 R1 ; ; C "0", H "0", Bits 4-7 = 3, bits 0-3 = C, R1 3CH R1 3CH + 06
If an addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using the standard binary arithmetic: 0001 + 0010 0011 0101 0111 1100 15 27 =3CH
The DA instruction adjusts this result so that the correct BCD representation is obtained: 0011 + 0000 0100 1100 0110 0010 =42
Assuming the same values given above, the statements SUB DA 27H,R0 @R1 ; ; C "0", H "0", Bits 4-7 = 3, bits 0-3 = 1 @R1 31-0
leave the value 31 (BCD) in the address 27H (@R1).
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DEC -- Decrement
DEC Operation: dst dst dst-1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Examples: Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH Opcode (Hex) 00 01 Addr Mode dst R IR
In the first example, if the working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.
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DECW -- Decrement Word
DECW Operation: dst dst dst - 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes opc dst 2 Cycles 8 8 Examples: Opcode (Hex) 80 81 Addr Mode dst RR IR
Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H: DECW DECW RR0 @R2 R0 = 12H, R1 = 33H Register 30H = 0FH, register 31H = 20H
In the first example, the destination register R0 contains the value 12H and the register R1 the value 34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H.
NOTE: A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, it is recommended to use DECW as shown in the following example.
LOOP LD OR JR
DECW R2,R1 R2,R0 NZ,LOOP
RR0
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DI -- Disable Interrupts
DI Operation: SYM (0) 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: Format: Bytes opc Example: Given: SYM = 01H: DI If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing. 1 Cycles 4 Opcode (Hex) 8F No flags are affected.
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DIV -- Divide (Unsigned)
DIV Operation: dst,src dst / src dst (UPPER) REMAINDER dst (LOWER) QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the 8 destination. When the quotient is 2 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers. Flags: C: Set if the V flag is set and the quotient is between 2 and 2 -1; cleared otherwise. Z: Set if the divisor or the quotient = "0"; cleared otherwise. S: Set if MSB of the quotient = "1"; cleared otherwise. V: Set if the quotient is 2 or if the divisor = "0"; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes opc src dst 3 Cycles 2 /10 * 2 /10 *
6 6 6 8 8 9
Opcode (Hex) 94 95
Addr Mode dst src RR RR R IR
2 /10 * 96 RR IM * Execution takes 10 cycles if the divide-by-zero 6 is attempted, otherwise, it takes 2 cycles. Examples: Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H: DIV RR0,R2 DIV RR0,@R2 DIV RR0,#20H R0 = 03H, R1 = 40H R0 = 03H, R1 = 20H R0 = 03H, R1 = 80H
In the first example, the destination working register pair RR0 contains the values 10H (R0) and 03H (R1), and the register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1).
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DJNZ -- Decrement and Jump if Non-Zero
DJNZ Operation: r,dst rr-1 If r 0, PC PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is + 127 to - 128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement.
NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0 or SRP1 instruction.
Flags: Format:
No flags are affected.
Bytes r | opc dst 2
Cycles 8 (jump taken) 8 (no jump)
Opcode (Hex) rA r = 0 to F
Addr Mode dst RA
Example:
Given: R1 = 02H and LOOP is the label of a relative address: SRP DJNZ #0C0H R1,LOOP
DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, the working register R1 contains the value 02H, and LOOP is the label for a relative address. The statement "DJNZ R1, LOOP" decrements the register R1 by one, leaving the value 01H. Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label.
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EI -- Enable Interrupts
EI Operation: SYM (0) 1 The EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have the highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when the EI instruction is executed. Flags: Format: Bytes opc Example: Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.) 1 Cycles 4 Opcode (Hex) 9F No flags are affected.
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ENTER -- Enter
ENTER Operation: SP SP - 2 @SP IP IP PC PC @IP IP IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two. Flags: Format: Bytes opc Example: 1 Cycles 14 Opcode (Hex) 1F No flags are affected.
The diagram below shows an example of how to use an ENTER statement.
Before After Address Data IP 0043 Address PC 0040 Data PC 0110 Address Data
Address Data IP 0050
0022
40 Enter 1F 41 Address H 01 42 Address L 10 43 Address H
0020
40 Enter 1F 41 Address H 01 42 Address L 10 43 Address H 110 Routine Memory
22
Data Stack
Memory
20 21 22
IPH 00 IPL 50 Data Stack
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EXIT -- Exit
EXIT Operation: IP SP PC IP @SP SP + 2 @IP IP + 2
This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: Format: Bytes opc Example: 1 Cycles 16 Opcode (Hex) 2F No flags are affected.
The diagram below shows an example of how to use an EXIT statement.
Before After Address Data IP 0043 Address PC 0040 50 51 0020 140 Exit Memory 22 Data Stack Memory PCL old PCH 60 00 0022 Data PC 0110 60 Main Address Data
Address IP 0050
Data
20 21 22
IPH 00 IPL 50 Data Stack
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IDLE -- Idle Operation
IDLE Operation: (See description) The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode dst src - - No flags are affected.
Example:
The instruction IDLE stops the CPU clock but it does not stop the system clock.
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INC -- Increment
INC Operation: dst dst dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes dst | opc 1 Cycles 4 Opcode (Hex) rE r = 0 to F opc dst 2 4 4 Examples: 20 21 R IR Addr Mode dst r
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC R0 INC 00H INC @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H
In the first example, if the destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The second example shows the effect an INC instruction has on the register at the location 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of the register 1BH from 0FH to 10H.
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INSTRUCTION SET
INCW -- Increment Word
INCW Operation: dst dst dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes opc dst 2 Cycles 8 8 Examples: Opcode (Hex) A0 A1 Addr Mode dst RR IR
Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH: INCW INCW RR0 @R1 R0 = 1AH, R1 = 03H Register 02H = 10H, register 03H = 00H
In the first example, the working register pair RR0 contains the value 1AH in the register R0 and 02H in the register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in the register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of the general register 03H from 0FFH to 00H and the register 02H from 0FH to 10H.
NOTE: A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To avoid this problem, it is recommended to use the INCW instruction as shown in the following example:
LOOP:
INCW LD OR JR
RR0 R2,R1 R2,R0 NZ,LOOP
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IRET -- Interrupt Return
IRET Operation: IRET (Normal) FLAGS @SP SP SP + 1 PC @SP SP SP + 2 SYM(0) 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine. Flags: Format: IRET (Normal) opc IRET (Fast) opc Example: Bytes 1 Bytes 1 Cycles 12 Cycles 6 Opcode (Hex) BF Opcode (Hex) BF All flags are restored to their original settings (that is, the settings before the interrupt occurred). iRET (Fast) PC IP FLAGS FLAGS' FIS 0
In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled. When an interrupt occurs, the program counter and the instruction pointer are swapped. This causes the PC to jump to the address 100H and the IP to keep the return address. The last instruction in the service routine is normally a jump to IRET at the address FFH. This loads the instruction pointer with 100H "again" and causes the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H.
0H FFH 100H IRET Interrupt Service Routine JP to FFH FFFFH
NOTE:
In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last tow instruction. The IRET cannot be immediately proceeded by an instruction which clears the interrupt status (as with a reset of the IPR register).
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JP -- JUMP
JP JP Operation: cc,dst (Conditional) dst (Unconditional) If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true, otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. Flags: Format: (1) Bytes
(2)
No flags are affected.
Cycles 8
Opcode (Hex) ccD cc = 0 to F
Addr Mode dst DA
cc | opc
dst
3
opc
dst
2
8
30
IRR
NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the 3-byte instruction format (conditional jump), the condition code and the OPCODE are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H JP C,LABEL_W JP @00H LABEL_W = 1000H, PC = 1000H PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
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JR -- Jump Relative
JR Operation: cc,dst If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter, otherwise, the instruction following the JR instruction is executed. (See the list of condition codes at the beginning of this chapter). The range of the relative address is +127, -128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: Format: Bytes
(note)
No flags are affected.
Cycles 6
Opcode (Hex) ccB cc = 0 to F
Addr Mode dst RA
cc | opc
dst
2
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits in length.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H
If the carry flag is set (that is, if the condition code is "true"), the statement "JR C,LABEL_X" will pass control to the statement whose address is currently in the program counter. Otherwise, the program instruction following the JR will be executed.
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LD -- LOAD
LD Operation: dst,src dst src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: Format: Bytes dst | opc src 2 Cycles 4 4 src | opc dst 2 4 Opcode (Hex) rC r8 r9 r = 0 to F opc dst | src 2 4 4 opc src dst 3 6 6 opc dst src 3 6 6 opc opc opc src dst | src src | dst dst x x 3 3 3 6 6 6 C7 D7 E4 E5 E6 D6 F5 87 97 r Ir R R R IR IR r x [r] lr r R IR IM IM R x [r] r Addr Mode dst src r r R IM R r No flags are affected.
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LD -- Load
LD Examples: (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH
LD R0,#LOOP[R1] LD #LOOP[R0],R1
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LDB -- Load Bit
LDB LDB Operation: dst,src.b dst.b,src dst(0) src(b) or dst(b) src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: Format: Bytes opc opc
dst | b | 0
No flags are affected.
Cycles 6 6
Opcode (Hex) 47 47
Addr Mode dst src r0 Rb Rb r0
src dst
3 3
src | b | 1
NOTE: In the second byte of the instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the LSB address value is one bit in length.
Examples:
Given: R0 = 06H and general register 00H = 05H: LDB LDB R0,00H.2 00H.0,R0 R0 = 07H, register 00H = 05H R0 = 06H, register 00H = 04H
In the first example, the destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H register into bit zero of the R0 register, leaving the value 07H in the register R0. In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of the register R0 to the specified bit (bit zero) of the destination register, leaving 04H in the general register 00H.
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LDC/LDE -- Load Memory
LDC LDE Operation: dst,src dst,src dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes "Irr" or "rr" values an even number for program memory and an odd number for data memory. Flags: Format: Bytes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. opc opc opc opc opc opc opc opc opc opc dst | src
src | dst dst | src src | dst dst | src src | dst dst | 0000 src | 0000 dst | 0001 src | 0001 2 2
No flags are affected.
Cycles
10 10 12 12 14 14 14 14 14 14
Opcode (Hex)
C3 D3 E7 F7 A7 B7 A7 B7 A7 B7
Addr Mode dst src
r Irr r XS [rr] r XL [rr] r DA r DA Irr r XS [rr] r XL [rr] r DA r DA r
XS XS XLL XLL DAL DAL DAL DAL XLH XLH DAH DAH DAH DAH
3 3 4 4 4 4 4 4
NOTES: 1. The source (src) or the working register pair [rr] for formats 5 and 6 cannot use the register pair 0-1. 2. For the formats 3 and 4, the destination "XS [rr]" and the source address "XS [rr]" are both one byte. 3. For the formats 5 and 6, the destination "XL [rr] and the source address "XL [rr]" are both two bytes. 4. The DA and the r source values for the formats 7 and 8 are used to address program memory. The second set of values, used in the formats 9 and 10, are used to address data memory. 5. LDE instruction can be used to read/write the data of 64-Kbyte data memory.
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LDC/LDE -- Load Memory
LDC/LDE Examples: (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 ; R0 contents of program memory location 0104H; ; R0 = 1AH, R2 = 01H, R3 = 04H LDE R0,@RR2 ; R0 contents of external data memory location 0104H; ; R0 = 2AH, R2 = 01H, R3 = 04H LDC @RR2,R0 ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2); R0, R2, R3 no change LDE @RR2,R0 ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2); R0, R2, R3 no change LDC R0,#01H[RR2] ; R0 contents of program memory location 0105H ; (01H + RR2); R0 = 6DH, R2 = 01H, R3 = 04H LDE R0,#01H[RR2] ; R0 contents of external data memory location 0105H ; (01H + RR2); R0 = 7DH, R2 = 01H, R3 = 04H LDC #01H[RR2],R0 ; 11H (contents of R0) is loaded into program memory location ; 0105H (01H + 0104H) LDE #01H[RR2],R0 ; 11H (contents of R0) is loaded into external data memory ; location 0105H (01H + 0104H) LDC R0,#1000H[RR2] ; R0 contents of program memory location 1104H ; (1000H + 0104H); R0 = 88H, R2 = 01H, R3 = 04H LDE R0,#1000H[RR2] ; R0 contents of external data memory location 1104H ; (1000H + 0104H); R0 = 98H, R2 = 01H, R3 = 04H LDC R0,1104H ; R0 contents of program memory location 1104H ; R0 = 88H LDE R0,1104H ; R0 contents of external data memory location 1104H; ; R0 = 98H LDC 1105H,R0 ; 11H (contents of R0) is loaded into program memory location ; 1105H; (1105H) 11H LDE 1105H,R0 ; 11H (contents of R0) is loaded into external data memory ; location 1105H; (1105H) 11H
The LDC and the LDE instructions are not supported by masked ROM type devices.
NOTE:
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LDCD/LDED -- Load Memory and Decrement
LDCD LDED Operation: dst,src dst,src dst src rr rr - 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD refers to program memory and LDED refers to external data memory. The assembler makes "Irr" an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc Examples: dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr No flags are affected.
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one; ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 - 1) ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 RR6 - 1); ; R8 = 0DDH, R6 = 10H, R7 = 32H
LDED
R8,@RR6
NOTE:
LDED instruction can be used to read/write the data of 64-Kbyte data memory.
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LDCI/LDEI -- Load Memory and Increment
LDCI LDEI Operation: dst,src dst,src dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes "Irr" an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc Examples: dst | src 2 Cycles 10 Opcode (Hex) E3 Addr Mode dst src r Irr No flags are affected.
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1); ; R8 = 0CDH, R6 = 10H, R7 = 34H ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 RR6 + 1); ; R8 = 0DDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
NOTE:
LDEI instruction can be used to read/write the data of 64-Kbyte data memory.
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LDCPD/LDEPD -- Load Memory with Pre-Decrement
LDCPD LDEPD Operation: dst,src dst,src rr rr - 1 dst src These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected. LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes "Irr" an even number for program memory and an odd number for external data memory. Flags: Format: Bytes opc Examples: src | dst 2 Cycles 14 Opcode (Hex) F2 Addr Mode dst src Irr r No flags are affected.
Given: R0 = 77H, R6 = 30H, and R7 = 00H: LDCPD @RR6,R0 ; (RR6 RR6 - 1) ; 77H (the contents of R0) is loaded into program memory ; location 2FFFH (3000H - 1H); ; R0 = 77H, R6 = 2FH, R7 = 0FFH ; (RR6 RR6 - 1) ; 77H (the contents of R0) is loaded into external data memory ; location 2FFFH (3000H - 1H);
LDEPD
@RR6,R0
NOTE:
LDEPD instruction can be used to read/write the data of 64-Kbyte data memory.
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LDCPI/LDEPI -- Load Memory with Pre-Increment
LDCPI LDEPI Operation: dst,src dst,src rr rr + 1 dst src These instructions are used for block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected. LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes "Irr" an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc Examples: src | dst 2 Cycles 14 Opcode (Hex) F3 Addr Mode dst src Irr r No flags are affected.
Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH: LDCPI @RR6,R0 ; (RR6 bRR6 + 1) ; 7FH (the contents of R0) is loaded into program memory ; location 2200H (21FFH + 1H); ; R0 = 7FH, R6 = 22H, R7 = 00H ; (RR6 bRR6 + 1) ; 7FH (the contents of R0) is loaded into external data memory ; location 2200H (21FFH + 1H); ; R0 = 7FH, R6 = 22H, R7 = 00H
LDEPI
@RR6,R0
NOTE:
LDEPI instruction can be used to read/write the data of 64-Kbyte data memory.
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LDW -- Load Word
LDW Operation: dst,src dst src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: Format: Bytes Cycles Opcode (Hex) C4 C5 C6 Addr Mode dst src RR RR RR RR IR IML No flags are affected.
opc
src
dst
3
8 8
opc Examples:
dst
src
4
8
Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H,and register 03H = 0FH LDW LDW LDW LDW LDW LDW RR6,RR4 00H,02H RR2,@R7 04H,@01H RR6,#1234H 02H,#0FEDH R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH R2 = 03H, R3 = 0FH, Register 04H = 03H, register 05H = 0FH R6 = 12H, R7 = 34H Register 02H = 0FH, register 03H = 0EDH
In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H and 03H into the destination word 00H and 01H. This leaves the value 03H in the general register 00H and the value 0FH in the register 01H. Other examples show how to use the LDW instruction with various addressing modes and formats.
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MULT -- Multiply (Unsigned)
MULT Operation: dst,src dst dst x src The 8-bit destination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Set if the result is > 255; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if MSB of the result is a "1"; cleared otherwise. V: Cleared. D: Unaffected. H: Unaffected. Format: Bytes opc src dst 3 Cycles 22 22 22 Examples: Opcode (Hex) 84 85 86 Addr Mode dst src RR RR RR R IR IM
Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H: MULT MULT MULT 00H, 02H 00H, @01H 00H, #30H Register 00H = 01H, register 01H = 20H, register 02H = 09H Register 00H = 00H, register 01H = 0C0H Register 00H = 06H, register 01H = 00H
In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16-bit product, 0120H, is stored in the register pair 00H, 01H.
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NEXT -- Next
NEXT Operation: PC @IP IP IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: Format: Bytes opc Example: 1 Cycles 10 Opcode (Hex) 0F No flags are affected.
The following diagram shows an example of how to use the NEXT instruction.
i h h pw h k hGo hGs hGo WX ZW wj WXZW WW[\ h [Z [[ [\ hGo hGs hGo k k
h pw WW[Z
k
wj
WXYW
[Z [[ [\
XYW
u t
XZW
y t
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NOP -- No Operation
NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to affect a timing delay of variable duration. No flags are affected.
Flags: Format:
Bytes opc Example: 1
Cycles 4
Opcode (Hex) FF
When the instruction NOP is executed in a program, no operation occurs. Instead, there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered.
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OR -- Logical OR
OR Operation: dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1", otherwise, a "0" is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc Examples: dst src 3 6 Opcode (Hex) 42 43 44 45 46 Addr Mode dst src r r R R R r lr R IR IM
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH
In the first example, if the working register R0 contains the value 15H and the register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in the destination register R0. Other examples show the use of the logical OR instruction with various addressing modes and formats.
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POP -- Pop from Stack
POP Operation: dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: Format: Bytes opc dst 2 Cycles 8 8 Examples: Opcode (Hex) 50 51 Addr Mode dst R IR No flags are affected.
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 00FCH Register 00H = 01H, register 01H = 55H, SP = 00FCH
In the first example, the general register 00H contains the value 01H. The statement "POP 00H" loads the contents of the location 00FBH (55H) into the destination register 00H and then increments the stack pointer by one. The register 00H then contains the value 55H and the SP points to the location 00FCH.
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POPUD -- Pop User Stack (Decrementing)
POPUD Operation: dst,src dst src IR IR - 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: Format: Bytes opc Example: src dst 3 Cycles 8 Opcode (Hex) 92 Addr Mode dst src R IR No flags are affected.
Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H: POPUD 02H,@00H Register 00H = 41H, register 02H = 6FH, register 42H = 6FH
If the general register 00H contains the value 42H and the register 42H the value 6FH, the statement "POPUD 02H,@00H" loads the contents of the register 42H into the destination register. The user stack pointer is then decremented by one, leaving the value 41H.
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POPUI --
POPUI Operation:
Pop User Stack (Incrementing)
dst,src dst src IR IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.
Flags: Format:
No flags are affected.
Bytes opc Example: src dst 3
Cycles 8
Opcode (Hex) 93
Addr Mode dst src R IR
Given: Register 00H = 01H and register 01H = 70H: POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H
If the general register 00H contains the value 01H and the register 01H the value 70H, the statement "POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (the register 00H) is then incremented by one, changing its value from 01H to 02H.
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PUSH -- Push to Stack
PUSH Operation: src SP SP - 1 @SP src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: Format: Bytes opc src 2 Cycles 8 (internal clock) 8 (external clock) 8 (internal clock) 8 (external clock) Examples: 71 IR Opcode (Hex) 70 Addr Mode dst R No flags are affected.
Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H: PUSH PUSH 40H @40H Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
In the first example, if the stack pointer contains the value 0000H, and the general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of the register 40H into the location 0FFFFH and adds this new value to the top of the stack.
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PUSHUD -- Push User Stack (Decrementing)
PUSHUD Operation: dst,src IR IR - 1 dst src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: Format: Bytes opc Example: dst src 3 Cycles 8 Opcode (Hex) 82 Addr Mode dst src IR R No flags are affected.
Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH: PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H
If the user stack pointer (the register 00H, for example) contains the value 03H, the statement "PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The 01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer.
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PUSHUI -- Push User Stack (Incrementing)
PUSHUI Operation: dst,src IR IR + 1 dst src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: Format: Bytes opc Example: dst src 3 Cycles 8 Opcode (Hex) 83 Addr Mode dst src IR R No flags are affected.
Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH: PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H
If the user stack pointer (the register 00H, for example) contains the value 03H, the statement "PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer.
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RCF -- Reset Carry Flag
RCF Operation: RCF C0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes opc Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero. 1 Cycles 4 Opcode (Hex) CF
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RET -- Return
RET Operation: PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement to be executed is the one that is addressed by the new program counter value. Flags: Format: Bytes opc Example: 1 Cycles 10 Opcode (Hex) AF No flags are affected.
Given: SP = 00FCH, (SP) = 101AH, and PC = 1234: RET PC = 101AH, SP = 00FEH
The RET instruction pops the contents of the stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in the location 00FEH (1AH) into the PC's low byte and the instruction at the location 101AH is executed. The stack pointer now points to the memory location 00FEH.
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RL -- Rotate Left
RL Operation: dst C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag, as shown in the figure below.
7 C 0
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Examples: Opcode (Hex) 90 91 Addr Mode dst R IR
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if the general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry (C) and the overflow (V) flags.
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RLC -- Rotate Left through Carry
RLC Operation: dst dst (0) C C dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C), and the initial value of the carry flag replaces bit zero.
7 C 0
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Examples: Opcode (Hex) 10 11 Addr Mode dst R IR
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if the general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register 00H, leaving the value 55H (01010101B). The MSB of the register 00H resets the carry flag to "1" and sets the overflow flag.
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RR -- Rotate Right
RR Operation: dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7 C 0
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Examples: Opcode (Hex) E0 E1 Addr Mode dst R IR
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if the general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and the overflow flag are also set to "1".
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RRC -- Rotate Right through Carry
RRC Operation: dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag, and the initial value of the carry flag replaces bit 7 (MSB).
7 C 0
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1". Z: Set if the result is "0" cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Examples: Opcode (Hex) C0 C1 Addr Mode dst R IR
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if the general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in the destination register 00H. The sign flag and the overflow flag are both cleared to "0".
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SB0 -- Select Bank 0
SB0 Operation: BANK 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file. Flags: Format: Bytes opc Example: 1 Cycles 4 Opcode (Hex) 4F No flags are affected.
The statement SB0 clears FLAGS.0 to "0", selecting the bank 0 register addressing.
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SB1 -- Select Bank 1
SB1 Operation: BANK 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file.
NOTE: Bank 1 is not implemented in some KS88-series microcontrollers.
Flags: Format:
No flags are affected.
Bytes opc Example: 1
Cycles 4
Opcode (Hex) 5F
The statement SB1 sets FLAGS.0 to "1", selecting the bank 1 register addressing (if bank 1 is implemented in the microcontroller's internla register file).
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SBC -- Subtract with Carry
SBC Operation: dst,src dst dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: C: Set if a borrow occurred (src > dst); cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow" Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc Examples: dst src 3 6 Opcode (Hex) 32 33 34 35 36 Addr Mode dst src r r R R R r lr R IR IM
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H, register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1"
In the first example, if the working register R1 contains the value 10H and the register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in the register R1.
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SCF -- Set Carry Flag
SCF Operation: C1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes opc Example: The statement SCF sets the carry flag to "1". 1 Cycles 4 Opcode (Hex) DF
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SRA -- Shift Right Arithmetic
SRA Operation: dst dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0-6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into the bit position 6.
7 C 6 0
Flags:
C: Set if the bit shifted from the LSB position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Examples: Opcode (Hex) D0 D1 Addr Mode dst R IR
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if the general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in the register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in the destination register 00H.
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SRP/SRP0/SRP1 -- Set Register Pointer
SRP SRP0 SRP1 Operation: src src src If src (1) = 1 and src (0) = 0 then: If src (1) = 0 and src (0) = 1 then: If src (1) = 0 and src (0) = 0 then: RP0 (3-7) src (3-7) RP1 (3-7) src (3-7) RP0 (4-7) src (4-7), RP0 (3) RP1 (3) 0 1 RP1 (4-7) src (4-7),
The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3-7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one. Flags: Format: Bytes opc Examples: src 2 Cycles 4 Opcode (Hex) 31 Addr Mode src IM No flags are affected.
The statement SRP #40H sets the register pointer 0 (RP0) at the location 0D6H to 40H and the register pointer 1 (RP1) at the location 0D7H to 48 H. The statement "SRP0 #50H" would set RP0 to 50H, and the statement "SRP1 #68H" would set RP1 to 68H.
NOTE:
Before execute the STOP instruction, You must set the STPCON register as "10100101b". Otherwise the STOP instruction will not execute.
6-80
S3C84BB/F84BB
INSTRUCTION SET
STOP -- Stop Operation
STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. No flags are affected.
Flags: Format:
Bytes opc 1
Cycles 4
Opcode (Hex) 7F
Addr Mode dst src - -
Example:
The statement STOP halts all microcontroller operations.
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INSTRUCTION SET
S3C84BB/F84BB
SUB -- Subtract
SUB Operation: dst,src dst dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Set if a "borrow" occurred; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc Examples: dst src 3 6 Opcode (Hex) 22 23 24 25 26 Addr Mode dst src r r R R R r lr R IR IM
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if he working register R1 contains the value 12H and if the register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in the destination register R1.
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INSTRUCTION SET
SWAP -- Swap Nibbles
SWAP Operation: dst dst (0 - 3) dst (4 - 7) The contents of the lower four bits and the upper four bits of the destination operand are swapped.
7 43 0
Flags:
C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Undefined. D: Unaffected. H: Unaffected.
Format: Bytes opc dst 2 Cycles 4 4 Examples: Opcode (Hex) F0 F1 Addr Mode dst R IR
Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H: SWAP SWAP 00H @02H Register 00H = 0E3H Register 02H = 03H, register 03H = 4AH
In the first example, if the general register 00H contains the value 3EH (00111110B), the statement "SWAP 00H" swaps the lower and the upper four bits (nibbles) in the 00H register, leaving the value 0E3H (11100011B).
6-83
INSTRUCTION SET
S3C84BB/F84BB
TCM -- Test Complement under Mask
TCM Operation: dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and the source operands are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc Examples: dst src 3 6 Opcode (Hex) 62 63 64 65 66 Addr Mode dst src r r R R R r lr R IR IM
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0"
In the first example, if the working register R0 contains the value 0C7H (11000111B) and the register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.
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INSTRUCTION SET
TM -- Test under Mask
TM Operation: dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and the source operands are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc Examples: dst src 3 6 Opcode (Hex) 72 73 74 75 76 Addr Mode dst src r r R R R r lr R IR IM
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1"
In the first example, if the working register R0 contains the value 0C7H (11000111B) and the register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.
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INSTRUCTION SET
S3C84BB/F84BB
WFI -- Wait for Interrupt
WFI Operation: The CPU is effectively halted before an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt. No flags are affected.
Flags: Format:
Bytes opc 1
Cycles 4n
Opcode (Hex) 3F
(n = 1, 2, 3, ... ) Example: The following sample program structure shows the sequence of operations that follow a "WFI" statement:
Main program
. . .
EI WFI (Next instruction)
(Enable global interrupt) (Wait for interrupt)
. . .
Interrupt occurs Interrupt service routine
. . .
Clear interrupt flag IRET Service routine completed
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INSTRUCTION SET
XOR -- Logical Exclusive OR
XOR Operation: dst,src dst dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different. Otherwise, a "0" bit is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 opc src dst 3 6 6 opc Examples: dst src 3 6 Opcode (Hex) B2 B3 B4 B5 B6 Addr Mode dst src r r R R R r lr R IR IM
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH
In the first example, if the working register R0 contains the value 0C7H and if the register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.
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INSTRUCTION SET
S3C84BB/F84BB
NOTES
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S3C84BB/F84BB
CLOCK CIRCUIT
CLOCK CIRCUIT
OVERVIEW
The clock frequency generated for the S3C84BB/F84BB by an external crystal can range from 1 MHz to 12 MHz. The maximum CPU clock frequency is 12 MHz. The XIN and XOUT pins connect the external oscillator or clock source to the on-chip clock circuit. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: -- External crystal or ceramic resonator oscillation source (or an external clock source) -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) -- System clock control register, CLKCON
C1
XIN S3C84BB/ F84BB
C2
XOUT
Figure 7-1. Main Oscillator Circuit (Crystal or Ceramic Oscillator)
7-1
CLOCK CIRCUIT
S3C84BB/F84BB
CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: -- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock. -- In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/ counters. Idle mode is released by a reset or by an external or internal interrupt.
Main-System Oscillator Circuit fxx STOP Instruction
1/8-1/4096 Frequency Dividing Circuit 1/1 1/2 1/8 1/16
PERI
CLKCON.4-.3
Selector 2 CPU
IDLE Instruction
Figure 7-2. System Clock Circuit Diagram
7-2
S3C84BB/F84BB
CLOCK CIRCUIT
SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in the bank 0 of set 1, address D4H. It is read/write addressable and has the following functions: -- Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fxx/8, fxx/2, or fxx/1.
System Clock Control Register (CLKCON) D4H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used (must keep always 0)
Not used (must keep always 0)
Divide-by selection bits for CPU clock frequency: 00 = fxx/16 01 = fxx/8 10 = fxx/2 11 = fxx/1 (non-divided)
Figure 7-3. System Clock Control Register (CLKCON)
7-3
CLOCK CIRCUIT
S3C84BB/F84BB
NOTES
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S3C84BB/F84BB
RESET and POWER-DOWN
RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C84BB/F84BB into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a reset operation is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both VDD and RESET are High level), the RESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values. In summary, the following sequence of events occurs during a reset operation: -- Interrupt is disabled. -- The watchdog function (basic timer) is enabled. -- Ports 0-8 are set to input mode. -- Peripheral control and data registers are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed.
NORMAL MODE RESET OPERATION In normal (masked ROM) mode, the Test pin is tied to VSS. A reset enables access to the 64-Kbyte on-chip ROM. NOTE To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON.
8-1
RESET and POWER-DOWN
S3C84BB/F84BB
HARDWARE RESET VALUES Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: -- A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. -- An "x" means that the bit value is undefined after a reset. -- A dash ("-") means that the bit is either not used or not mapped, but read 0 is the bit value.
Table 8-1. S3C84BB/F84BB Set 1 Register Values after RESET Register Name Timer B control register Timer B data register (high byte) Timer B data register (low byte) Basic timer control register Clock Control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer Mnemonic TBCON TBDATAH TBDATAL BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP Address Dec 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 Hex D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH 7 0 1 1 0 0 x 1 1 x x x x 0 x 0 0 6 0 1 1 0 0 x 1 1 x x x x 0 x - 0 Bit Values After RESET 5 0 1 1 0 0 x 0 0 x x x x 0 x - 0 4 0 1 1 0 0 x 0 0 x x x x 0 x x 0 3 0 1 1 0 0 x 0 1 x x x x 0 x x 0 2 0 1 1 0 0 x - - x x x x 0 x x 0 1 0 1 1 0 0 0 - - x x x x 0 x 0 0 0 0 1 1 0 0 0 - - x x x x 0 x 0 0
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RESET and POWER-DOWN
Table 8-2. S3C84BB/F84BB Set 1, Bank 0 Register Values after RESET Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Timer A/1 interrupt pending register Timer A control register Timer A data register Timer A counter register Port 8 control register (high byte) Port 8 control register (low byte) Port 8 interrupt/pending register Port 0 control register Port 1 control register Port 2 control register (high byte) Port 2 control register (low byte) Port 3 control register (high byte) Port 3 control register (low byte) Port 4 control register (high byte) Port 4 control register (low byte) Port 5 control register (high byte) Port 5 control register (low byte) Port 4 interrupt control register Port 4 interrupt/pending register Mnemonic P0 P1 P2 P3 P4 P5 P6 P7 P8 TINTPND TACON TADATA TACNT P8CONH P8CONL P8INTPND P0CON P1CON P2CONH P2CONL P3CONH P3CONL P4CONH P4CONL P5CONH P5CONL P4INT P4INTPND BTCNT IPR Address Dec 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 253 255 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FDH FFH 7 0 0 0 0 0 0 0 0 0 - 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x 6 0 0 0 0 0 0 0 0 0 - 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x Bit Values After Reset 5 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 4 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 3 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x
Location FCH is factory use only Basic timer counter register Interrupt priority register Location FEH is not mapped
8-3
RESET and POWER-DOWN
S3C84BB/F84BB
Table 8-3. S3C84BB/F84BB Set 1, Bank 1 Register Values after RESET Register Name SIO data register SIO Control register UART0 data register UART0 control register UART0 baud rate data register UART0,1 pending register Timer 1(0) data register (high byte) Timer 1(0) data register (low byte) Timer 1(1) data register (high byte) Timer 1(1) data register (low byte) Timer 1(0) control register Timer 1(1) control register Timer 1(0) counter register(high byte) Timer 1(0) counter register(low byte) Timer 1(1) counter register(high byte) Timer 1(1) counter register(low byte) Timer C(0) data register Timer C(1) data register Timer C(0) control register Timer C(1) control register SIO prescaler control register Port 7 control register D/A converter data register A/D, D/A converter control register A/D converter data register(high byte) A/D converter data register(low byte) UART1 data register UART1 control register UART1 baud rate data register Flash memory control register Pattern generation control register Pattern generation data register Mnemonic SIODATA SIOCON UDATA0 UARTCON0 BRDATA0 UARTPND T1DATAH0 T1DATAL0 T1DATAH1 T1DATAL1 T1CON0 T1CON1 T1CNTH0 T1CNTL0 T1CNTH1 T1CNTL1 TCDATA0 TCDATA1 TCCON0 TCCON1 SIOPS P7CON DADATA ADACON ADDATAH ADDATAL UDATA1 UARTCON1 BRDATA1 FMCON PGCON PGDATA Address Dec 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH 7 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 - 0 6 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 - 0 Bit Values After Reset 5 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 - 0 4 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 - 0 3 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 2 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0
8-4
S3C84BB/F84BB
RESET and POWER-DOWN
POWER-DOWN MODES
STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 A. All system functions stop when the clock "freezes," but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by interrupts. NOTE Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage. Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H (and 0101H). Using an External Interrupt to Release Stop Mode External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode. The external interrupts in the S3F84BB interrupt structure that can be used to release Stop mode are: -- External interrupts P4.0/INT0-P4.7/INT7, P8.4/INT8 and P8.5/INT9 Please note the following conditions for Stop mode release: -- If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged. -- If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. -- When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains unchanged and the currently selected clock value is used. -- The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. Using an internal Interrupt to Release Stop Mode Activate any enabled interrupt, causing stop mode to be released. Other things are same as using external interrupt.
8-5
RESET and POWER-DOWN
S3C84BB/F84BB
IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered. There are two ways to release idle mode: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4 and CLKCON.3 are cleared to `00B'. If interrupts are masked, a reset is the only way to release idle mode. 2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed.
8-6
S3C84BB/F84BB
I/O PORTS
I/O PORTS
OVERVIEW
The S3C84BB/F84BB microcontroller has nine bit-programmable I/O ports, P0-P8. The port 8 are 6-bit ports and the others are 8-bit ports. This gives a total of 70 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. Table 9-1 gives you a general overview of the S3C84BB/F84BB I/O port functions. Table 9-1. S3C84BB/F84BB Port Configuration Overview Port 0 Configuration Options Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P0.0-P0.7 can be used as the PG output port (PG0-PG7). Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P2.0~P2.7 can be used as I/O for TIMERA, TIMERB, DAC, SIO Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P3.0~P3.7 can be used as I/O for TIMERC0/C1, TIMER10/11 Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. P4.0-P4.7 can alternately be used as inputs for external interrupts INT0-INT7, respectively (with noise filters and interrupt controller) Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. Alternately, P5.0~P5.3 can be used as I/O for serial port UART0, UART1, respectively. N-channel, open-drain output only port. General-purpose digital input ports. Alternatively used as analog input pins for A/D converter modules. Bit programmable port; input or output mode selected by software; input or push-pull output. Software assignable pull-up. P8.4, P8.5 can alternately be used as inputs for external interrupts INT8, INT9, respectively (with noise filters and interrupt controller)
1 2
3
4
5
6 7 8
9-1
I/O PORTS
S3C84BB/F84BB
PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all five S3C84BB/F84BB I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, 5, 6, 7 and 8 have the general format shown in Table 9-2. Table 9-2. Port Data Register Summary Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Mnemonic P0 P1 P2 P3 P4 P5 P6 P7 P8 Decimal 224 225 226 227 228 229 230 231 232 Hex E0H E1H E2H E3H E4H E5H E6H E7H E8H Location Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
9-2
S3C84BB/F84BB
I/O PORTS
PORT 0 Port 0 is an 8-bit I/O Port that you can use two ways: -- General-purpose I/O -- Alternative function: PGOUT7-PGOUT0 Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H in set 1, bank 0. Port 0 Control Register (P0CON) Port 0 pins are configured individually by bit-pair settings in one control registers located in set 1, bank 0: P0CON (F0H). When programming the port, please remember that any alternative peripheral I/O function you configure using the port 0 control registers must also be enabled in the associated peripheral module.
9-3
I/O PORTS
S3C84BB/F84BB
Port 0 Control Register (P0CON) F0H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P0.7/P0.6/ P0.3/P0.2/ P0.1/ P0.5/P0.4/ PGOUT[3:2] PGOUT[1] PGOUT[7:4] .7 .6 bit/P0.7/P0.6/P0.5/P0.4 00 01 10 11
P0.0/ PGOUT[0]
Input mode Input mode, pull-up Push-pull output Alternative function mode(PGOUT[7:4])
.5 .4 bit/P0.3/P0.2 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative function mode(PGOUT[3:2])
.3 .2 bit/P0.1 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative function mode(PGOUT[1])
.1 .0 bit/P0.0 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative function mode(PGOUT[0])
Figure 9-1. Port 0 Control Register (P0CON)
9-4
S3C84BB/F84BB
I/O PORTS
PORT 1 Port 1 is an 8-bit I/O Port that you can use one ways: -- General-purpose I/O Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location E1H in set 1, bank 0. Port 1 Control Register (P1CON) Port 1 pins are configured individually by bit-pair settings in one control registers located in set 1, bank 0: P1CON (F1H). When programming the port, please remember that any alternative peripheral I/O function you configure using the port 1 control registers must also be enabled in the associated peripheral module.
9-5
I/O PORTS
S3C84BB/F84BB
Port 1 Control Register (P1CON) F1H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P1.7/P1.6
P1.5/P1.4
P1.3/P1.2
P1.0/P1.0
.7 .6 bit/P1.7/P1.6 00 01 1x Input mode Input mode, pull-up Push-pull output
.5 .4 bit/P1.5/P1.4 00 01 1x Input mode Input mode, pull-up Push-pull output
.3 .2 bit/P1.3/P1.2 00 01 1x Input mode Input mode, pull-up Push-pull output
.1 .0 bit/P1.1//P.0 00 01 1x Input mode Input mode, pull-up Push-pull output
Figure 9-2. Port 1 Control Register (P1CON)
9-6
S3C84BB/F84BB
I/O PORTS
PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E2H in set 1, bank 0. P2.0-P2.7 can serve as inputs, outputs (push pull) or you can configure the following alternative functions: -- Low-byte pins (P2.0-P2.3): DAOUT, SCK, SI, SO -- High-byte pins (P2.4-P2.7): TAOUT, TACAP, TACK, TBPWM Port 2 Control Register (P2CONH, P2CONL) Port 2 has two 8-bit control registers: P2CONH for P2.4-P2.7 and P2CONL for P2.0-P2.3. A reset clears the P2CONH and P2CONL registers to "00H", configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull) and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 2 control registers must also be enabled in the associated peripheral module.
9-7
I/O PORTS
S3C84BB/F84BB
Port 2 Control Register, High Byte (P2CONH) F2H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.4/TBPWM P2.5/TACK P2.6/TACAP P2.7/TAOUT .7 .6 bit/P2.7/TAOUT 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative output mode(TAOUT)
.5 .4 bit/P2.6/TACAP 00 01 10 11 Input mode(TACAP) Input mode, pull-up(TACAP) Push-pull output Alternative output mode(Not used)
.3 .2 bit/P2.5/TACK 00 01 10 11 Input mode(TACK) Input mode, pull-up(TACK) Push-pull output Alternative output mode(Not used)
.1 .0 bit/P2.4/TBPWM 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative output mode(TBPWM)
NOTE:
When use this port 2, user must be care of the pull-up resistance status.
Figure 9-3. Port 2 High-Byte Control Register (P2CONH)
9-8
S3C84BB/F84BB
I/O PORTS
Port 2 Control Register, Low Byte (P2CONL) F3H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P2.0/SO P2.1/SI P2.3/ DAOUT 00 01 10 11 P2.2/SCK
.7 .6 bit/P2.3/DAOUT Input mode Input mode, pull-up Push-pull output Alternative output mode(DAOUT)
.5 .4 bit/P2.2/SCK 00 01 10 11 Input mode(SCK input) Input mode, pull-up(SCK input) Push-pull output Alternative output mode(SCK output)
.3 .2 bit/P2.1/SI 00 01 10 11 Input mode(SI) Input mode, pull-up(SI) Push-pull output Alternative output mode(Not used)
.1 .0 bit/P2.0/SO 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative output mode(SO)
NOTE:
When use this port 2, user must be care of the pull-up resistance status.
Figure 9-4. Port 2 Low-Byte Control Register (P2CONL)
9-9
I/O PORTS
S3C84BB/F84BB
PORT 3 Port 3 is an 8-bit I/O port that can be used for general-purpose I/O. The pins are accessed directly by writing or reading the port 3 data register, P3 at location E3H in set 1, bank 0. P3.7-P3.0 can serve as inputs, outputs (push pull) or you can configure the following alternative functions: -- Low-byte pins (P3.0-P3.3): T1CAP1, T1CAP0, T1CK1, T1CK0 -- High-byte pins (P3.4-P3.7): TCOUT1, TCOUT0, T1OUT1, T1OUT0 To individually configure the port 3 pins P3.0-P3.7, you make bit-pair settings in two control registers located in set 1, bank 0: P3CONL (low byte, F5H) and P3CONH (high byte, F4H). Port 3 Control Registers (P3CONH, P3CONL) Two 8-bit control registers are used to configure port 3 pins: P3CONL (F5H, set 1, Bank 0) for pins P3.0-P3.3 and P3CONH (F4H, set 1, Bank 0) for pins P3.4-P3.7. Each byte contains four bit-pairs and each bit-pair configures one pin of port 3.
9-10
S3C84BB/F84BB
I/O PORTS
Port 3 Control Register, High Byte (P3CONH) F4H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P3.4/T1OUT0 P3.5/T1OUT1 P3.6/TCOUT0 P3.7/TCOUT1 .7 .6 bit : P3.7/TCOUT1 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative function(TCOUT1)
.5 .4 bit : P3.6/TCOUT0 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative function(TCOUT0)
.3 .2 bit : P3.5/T1OUT1 00 01 10 11 Input mode Input mode, pull-up Push-pull outputt Alternative function(T1OUT1)
.1 .0 bit : P3.4/T1OUT0 00 01 10 11 Input mode Input mode, pull-up Push-pull outputt Alternative function(T1OUT0)
Figure 9-5. Port 3 High-Byte Control Register (P3CONH)
9-11
I/O PORTS
S3C84BB/F84BB
Port 3 Control Register, Low Byte (P3CONL) F5H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P3.0/T1CK0 P3.1/T1CK1 P3.2/T1CAP0 P3.3/T1CAP1 .7 .6 bit/P3.3/T1CAP1 00 01 1x Input mode(T1CAP1) Input mode, pull-up(T1CAP1) Push-pull output
.5 .4 bit/P3.2/T1CAP0 00 01 1x Input mode(T1CAP0) Input mode, pull-up(T1CAP0) Push-pull output
.3 .2 bit/P3.1/T1CK1 00 01 1x Input mode(T1CK1) Input mode, pull-up(T1CK1) Push-pull output
.1 .0 bit/P3.0/T1CK0 00 01 1x Input mode(T1CK0) Input mode, pull-up(T1CK0) Push-pull output
Figure 9-6. Port 3 Low-Byte Control Register (P3CONL)
9-12
S3C84BB/F84BB
I/O PORTS
PORT 4 Port 4 is an 8-bit I/O Port that you can use two ways: -- General-purpose I/O -- External interrupt inputs for INT0-INT7 Port 4 is accessed directly by writing or reading the port 4 data register, P4 at location E4H in set 1, bank 0. Port 4 Control Register (P4CONH, P4CONL) Port 4 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0: P4CONL (low byte, F7H) and P4CONH (high byte, F6H). When you select output mode, a push-pull circuit is configured. In input mode, three different selections are available: -- Schmitt trigger input with interrupt generation on falling signal edges. -- Schmitt trigger input with interrupt generation on rising signal edges. -- Schmitt trigger input with pull-up resistor and interrupt generation on falling signal edges. Port 4 Interrupt Enable and Pending Registers (P4INT, P4INTPND) To process external interrupts at the port 4 pins, two additional control registers are provided: the port 4 interrupt enable register P4INT (FAH, set 1, bank 0) and the port 4 interrupt pending register P4INTPND (FBH, set 1, bank 0). The port 4 interrupt pending register P4INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P4INTPND register at regular intervals. When the interrupt enable bit of any port 4 pin is "1", a rising or falling signal edge at that pin will generate an interrupt request. The corresponding P4INTPND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must clear the pending condition by writing a "0" to the corresponding P4INTPND bit.
9-13
I/O PORTS
S3C84BB/F84BB
Port 4 Control Register, High Byte (P4CONH) F6H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.7/ INT7
P4.6/ INT6
P4.5/ INT5
P4.4/ INT4
.7 .6 bit/P4.7INT7 00 01 10 11 Input mode; (falling edge interrupt) Input mode; (rising edge interrupt) Input mode, pull-up; (falling edge interrupt) Push-pull output
.5 .4 bit/P4.6/INT6 Input mode; (falling edge interrupt) 00 Input mode; (rising edge interrupt) 01 Input mode, pull-up; (falling edge interrupt) 10 Push-pull output 11 .3 .2 bit/P4.5/INT5 Input mode; (falling edge interrupt) 00 Input mode; (rising edge interrupt) 01 Input mode, pull-up; (falling edge interrupt) 10 Push-pull output 11 .1 .0 bit/P4.4/INT4 Input mode; (falling edge interrupt) 00 Input mode; (rising edge interrupt) 01 Input mode, pull-up; (falling edge interrupt) 10 Push-pull output 11
Figure 9-7. Port 4 High-Byte Control Register (P4CONH)
9-14
S3C84BB/F84BB
I/O PORTS
Port 4 Control Register, Low Byte (P4CONL) F7H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P4.3/ INT3
P4.2/ INT2
P4.1/ INT1
P4.0/ INT0
.7 .6 bit/P4.3/INT3 00 01 10 11 Input mode; (falling edge interrupt) Input mode; (rising edge interrupt) Input mode, pull-up; (falling edge interrupt) Push-pull output
.5 .4 bit/P4.2/INT2 Input mode; (falling edge interrupt) 00 Input mode; (rising edge interrupt) 01 Input mode, pull-up; (falling edge interrupt) 10 Push-pull output 11 .3 .2 bit/P4.1/INT1 Input mode; (falling edge interrupt) 00 Input mode; (rising edge interrupt) 01 Input mode, pull-up; (falling edge interrupt) 10 Push-pull output 11 .1 .0 bit/P4.0/INT0 Input mode; (falling edge interrupt) 00 Input mode; (rising edge interrupt) 01 Input mode, pull-up; (falling edge interrupt) 10 Push-pull output 11
Figure 9-8. Port 4 Low-Byte Control Register (P4CONL)
9-15
I/O PORTS
S3C84BB/F84BB
Port 4 Interrupt Control Register (P4INT) FAH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
P4INT Bit Configuration Settings: 0 1 Interrupt disable Interrupt enable
Figure 9-9. Port 4 Interrupt Control Register (P4INT)
Port 4 Interrupt Pending Register (P4INTPND) FBH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0
P4INTPND Bit Configuration Settings: 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
Figure 9-10. Port 4 Interrupt Pending Register (P4INTPND)
9-16
S3C84BB/F84BB
I/O PORTS
PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E5H in set 1, bank 0. P5.7-P5.4 can serve as inputs, outputs (push pull or open-drain). P5.3-P5.0 can serve as inputs, outputs (push pull) or you can configure the following alternative functions: -- Low-byte pins (P5.3-P5.0): RxD0, TxD0, RxD1, TxD1 Port 5 Control Register (P5CONH, P5CONL) Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P5CONL for P5.0-P5.3. A reset clears the P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull, open-drain) and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 5 control registers must also be enabled in the associated peripheral module.
9-17
I/O PORTS
S3C84BB/F84BB
Port 5 Control Register, High Byte (P5CONH) F8H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.4 P5.5 P5.6 P5.7 .7 .6 bit : P5.7 00 01 10 11 Input mode Input mode, pull-up Push-pull output Open-drain mode
.5 .4 bit : P5.6 00 01 10 11 Input mode Input mode, pull-up Push-pull output Open-drain mode
.3 .2 bit : P5.5 00 01 10 11 Input mode Input mode, pull-up Push-pull output Open-drain mode
.1 .0 bit : P5.4 00 01 10 11 Input mode Input mode, pull-up Push-pull output Open-drain mode
Figure 9-11. Port 5 High-Byte Control Register (P5CONH)
9-18
S3C84BB/F84BB
I/O PORTS
Port 5 Control Register, Low Byte (P5CONL) F9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P5.3/ RxD0 00 01 10 11
P5.2/ TxD0
P5.1/ RxD1
P5.0/ TxD1
.7 .6 bit/P5.3/RxD0 Input mode(RxD0 input) Input mode, pull-up(RxD0 input) Push-pull output Alternative output mode(RxD0 output)
.5 .4 bit/P5.2/TxD0 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative output mode(TxD0 output)
.3 .2 bit/P5.1/RxD1 00 01 10 11 Input mode(RxD1 input) Input mode, pull-up(RxD1 input) Push-pull output Alternative output mode(RxD1 output)
.1 .0 bit/P5.0/TxD1 00 01 10 11 Input mode Input mode, pull-up Push-pull output Alternative output mode(TxD1 output)
Figure 9-12. Port 5 Low-Byte Control Register (P5CONL)
9-19
I/O PORTS
S3C84BB/F84BB
PORT 6 Port 6 is an 8-bit open drain output only port pins. Port 6 pins are accessed directly by writing the port6 data register, P6 at location E6H in set 1, bank 0.
9-20
S3C84BB/F84BB
I/O PORTS
PORT 7 Port 7 is an 8-bit Input port that you can use two ways: -- General-purpose Input -- Alternative function: ADC0-ADC7 input Port 7 is accessed directly by reading the port 7 data register, P7 at location E7H in set 1, bank 0. Port 7 Control Register (P7CON) Port 7 pins are configured individually by bit-pair settings in one control registers located in set 1, bank 1: P7CON (F5H). When programming the port, please remember that any alternative peripheral I function you configure using the port 7 control registers must also be enabled in the associated peripheral module.
9-21
I/O PORTS
S3C84BB/F84BB
Port 7 Control Register (P7CON) F5H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P7.7/ P7.6/ P7.5/ P7.4/ P7.3/ P7.2/ P7.1/ P7.0/ ADC7ADC6 ADC5ADC4 ADC3ADC2 ADC1ADC0 .7 bit : P7.7/ADC7 0 1 Input mode ADC input mode
.6 bit : P7.6/ADC6 0 1 Input mode ADC input mode
.5 bit : P7.5/ADC5 0 1 Input mode ADC input mode
.4 bit : P7.4/ADC4 0 1 Input mode ADC input mode
.3 bit : P7.3/ADC3 0 1 Input mode ADC input mode
.2 bit : P7.2/ADC2 0 1 Input mode ADC input mode
.1 bit : P7.1/ADC1 0 1 Input mode ADC input mode
.0 bit : P7.0/ADC0 0 1 Input mode ADC input mode
Figure 9-13. Port 7 Control Register (P7CON)
9-22
S3C84BB/F84BB
I/O PORTS
PORT 8 Port 8 is an 8-bit I/O Port that you can use two ways: -- General-purpose I/O -- External interrupt inputs for INT8-INT9 Port 8 is accessed directly by writing or reading the port 8 data register, P8 at location E8H in set 1, bank 0. Port 8 Control Register (P8CONH, P8CONL) Port 8 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0: P8CONL (low byte, EEH) and P8CONH (high byte, EDH). When you select output mode, a push-pull circuit is configured. In input mode, three different selections are available: -- Schmitt trigger input with interrupt generation on falling signal edges. -- Schmitt trigger input with interrupt generation on rising signal edges. -- Schmitt trigger input with pull-up resistor and interrupt generation on falling signal edges. Port 8 Interrupt Enable and Pending Registers (P8INTPND) To process external interrupts at the port 8 pins, one additional control register is provided: the port 8 interrupt enable register P8INTPND (EFH, set 1, bank 0). The port 8 interrupt pending register P8INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P8INTPND register at regular intervals. When the interrupt enable bit of any port 8 pin is "1", a rising or falling signal edge at that pin will generate an interrupt request. The corresponding P8INTPND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding P8INTPND bit.
9-23
I/O PORTS
S3C84BB/F84BB
Port 8 Control Register, High Byte (P8CONH) EDH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P8.5/ INT9
P8.4/ INT8
.3 .2 bit : P8.5/INT9 00 Input mode; (falling edge interrupt) 01 Input mode; (rising edge interrupt) 10 Input mode, pull-up; (falling edge interrupt) 11 Push-pull output .1 .0 bit : P8.4/INT8 00 Input mode; (falling edge interrupt) 01 Input mode; (rising edge interrupt) 10 Input mode, pull-up; (falling edge interrupt) 11 Push-pull output
Figure 9-14. Port 8 High-Byte Control Register (P8CONH)
9-24
S3C84BB/F84BB
I/O PORTS
Port 8 Control Register, Low Byte (P8CONL) EEH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
P8.3
P8.2
P8.1
P8.0
.7 .6 bit : P8.3 00 Input mode 01 Input mode, pull-up 1x Push-pull output .5 .4 bit : P8.2 00 Input mode 01 Input mode, pull-up 1x Push-pull output .3 .2 bit : P8.1 00 Input mode 01 Input mode, pull-up 1x Push-pull output .1 .0 bit : P8.0 00 Input mode 01 Input mode, pull-up 1x Push-pull output
Figure 9-15. Port 8 Low-Byte Control Register (P8CONL)
9-25
I/O PORTS
S3C84BB/F84BB
Port 8 Interrupt Pending Register (P8INTPND) EFH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
P8.5/ P8.4/ PND9 PND8
Not used
P8.5/ P8.4/ INT9 INT8
.5 bit : P8.5/PND9 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.4 bit : P8.4/PND8 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending
.1 bit : P8.5/INT9 0 1 Disable interrupt Enable interrupt
.0 bit : P8.4/INT8 0 1 Disable interrupt Enable interrupt
Figure 9-16. Port 8 Interrupt Pending Register (P8INTPND)
9-26
S3C84BB/F84BB
BASIC TIMER
BASIC TIMER
OVERVIEW
BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fxx divided by 4096, 1024 or 128) with multiplexer -- 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only) -- Basic timer control register, BTCON (set 1, D3H, read/write)
BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using register addressing mode. A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of fXX/4096. To disable the watchdog function, write the signature code '1010B' to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers, write a "1" to BTCON.0.
10-1
BASIC TIMER
S3C84BB/F84BB
Basic Timer Control Register (BTCON) D3H, Set 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Watchdog timer enable bit: 1010B = Disable watchdog function Other value = Enable watchdog function
Divider clear bit: 0 = No effect 1 = Clear divider Basic timer counter clear bit: 0 = No effect 1 = Clear BTCNT
Basic timer input clock selection bit: 00 = fxx/4096 01 = fxx/1024 10 = fxx/128 11 = fxx/16 (Not used)
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
S3C84BB/F84BB
BASIC TIMER
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. The MCU is reset whenever a basic timer counter overflow occurs, During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring, To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt. In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when stop mode is released: 1. During stop mode, a power-on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. When a BTCNT.4 overflow occurs, normal CPU operation resumes.
10-3
BASIC TIMER
S3C84BB/F84BB
Bit 1 Bits 3, 2
RESET or STOP Basic Timer Control Register (Write '1010xxxxB' to disable) Data Bus
fxx/4096 fxx/1024 fxx/128 R
Clear 8-Bit Up Counter (BTCNT, Read-Only) RESET
fxx
DIV
MUX
OVF
Start the CPU (note)
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
Figure 10-2. Basic Timer Block Diagram
10-4
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
8-BIT TIMER A/B/C(0/1)
8-BIT TIMER A
OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, you can select one of them using the appropriate TACON setting: -- Interval timer mode (Toggle output at TAOUT pin) -- Capture input mode with a rising or falling edge trigger at the TACAP pin -- PWM mode (TAPWM); PWM output shares its output port with TAOUT pin Timer A has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, or 64) with multiplexer -- External clock input pin (TACK) -- 8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA) -- I/O pins for capture input (TACAP) or PWM or match output (TAPWM, TAOUT) -- Timer A overflow interrupt (IRQ0, vector BAH) and match/capture interrupt (IRQ0, vector B8H) generation -- Timer A control register, TACON (set 1, bank0, EAH, read/write)
11-1
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
FUNCTION DESCRIPTION Timer A Interrupts (IRQ0, Vectors B8H and BAH) The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector BAH. TAINT also belongs to interrupt level IRQ0, but is assigned the separate vector address, B8H. A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A timer A match/capture interrupt, TAINT pending condition is also cleared by hardware when it has been serviced. Interval Timer Function The timer A module can generate an interrupt: the timer A match interrupt (TAINT). TAINT belongs to interrupt level IRQ0, and is assigned the separate vector address, B8H. When timer A match interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware. In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the TA reference data register, TADATA. The match signal generates a timer A match interrupt (TAINT, vector B8H) and clears the counter. If, for example, you write the value 10H to TADATA and 0AH to TACON, the counter will increment until it reaches 10H. At this point, the TA interrupt request is generated, the counter value is reset, and counting resumes. Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the TAPWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer A data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at FFH, and then continues incrementing from 00H. Although timer A overflow interrupt is occurred, this interrupt is not typically used in PWM-type applications. Instead, the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK * 256 . Capture Mode In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the TA data register. You can select rising or falling edges to trigger this operation. Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by setting the value of the timer A capture input selection bit in the port 2 control register, P2CONH, (set 1, bank 0, F2H). When P2CONH.5.4 is 00, the TACAP input or normal input is selected. When P2CONH.5.4 is set to 10, normal output is selected. Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded into the TA data register. By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the TACAP pin.
11-2
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON, to -- Select the timer A operating mode (interval timer, capture mode, or PWM mode) -- Select the timer A input clock frequency -- Clear the timer A counter, TACNT -- Enable the timer A overflow interrupt or timer A match/capture interrupt -- Clear timer A match/capture interrupt pending conditions TACON is located in set 1, Bank 0 at address EAH, and is read/write addressable using Register addressing mode. A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. The timer A overflow interrupt (TAOVF) is interrupt level IRQ0 and has the vector address BAH. When a timer A overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware. To enable the timer A match/capture interrupt (IRQ0, vector B8H), you must write TACON.1 to "1". To generate the exact time interval, you should write "1" to TACON.3 and "0" to TINTPND.0, which cleared counter and interrupt pending bit.
Timer A Control Register (TACON) EAH, Set 1, Bank 0, R/W, Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer A input clock selection bit: 00 = fxx/1024 01 = fxx/256 10 = fxx/64 11 = External clock (TACK) Timer A operating mode selection bit: 00 = Interval mode (TAOUT mode) 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF interrupt and match interrupt can occur)
Not used Timer A match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrrupt Timer A overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrrupt Timer A counter clear bit: 0 = No effect 1 = Clear the timer A counter ( when write)
NOTE: When the counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically. Pending bit of overflow and match/capture intterupt are located in TINTPND (E9, bank0) register.
Figure 11-1. Timer A Control Register (TACON)
11-3
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
BLOCK DIAGRAM
TACON.2 TACON.7-.6 fxx/1024 fxx/256 fxx/64 TACK Match M U X M U X Overflow Data Bus 8 8-bit Up-Counter (Read Only) Clear Pending TINTPND.1
TAOVF
TACON.3
TACON.1 Pending TINTPND.0
8-bit Comparator M U X
TAINT
TACAP
Timer A Buffer Reg
TAOUT(TAPWM)
TACON.5.4 Timer A Data Register (Read/Write) 8 Data Bus NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register.
TACON.5.4 PG output signal
Figure 11-2. Timer A Functional Block Diagram
11-4
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
8-BIT TIMER B
OVERVIEW The S3C84BB/F84BB micro-controller has an 8-bit counter called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal. Pending bit of timer B is cleared automatically by hardware. Timer B has two functions: -- As a normal interval timer, generating a timer B interrupt at programmed time intervals. -- To generate a programmable carrier pulse for a remote control signal at P2.4. BLOCK DIAGRAM
TBCON.6-.7
TBCON.2
PG output signal TBCON.0
fxx/1 fxx/2 fxx/4 fxx/8
M U X
CLK
8-Bit Down Counter
FF TB Underflow (TBUF) TBPWM(P2.4)
TBCON.1
Repeat Control
MUX
TBCON.3 IRQ1 (TBINT)
TBCON.4-.5 Timer B Data Low Byte Register 8 Data Bus Timer B Data High Byte Register 8 Data Bus
NOTE:
In case of setting TBCON.5-.4 at '10', the value of the TBDATAL register is loaded into the 8-bit counter when the operation of the timer B starts. And then if a underflow occurs in the counter, the value of the TBDATAH register is loaded with the value of the 8-bit counter. However, if the next borrow occurs, the value of the TBDATAL register is loaded with the value of the 8-bit counter. To output TBPWM as carrier wave, you have to set P2CONH.1-.0 as "11".
Figure 11-3. Timer B Functional Block Diagram
11-5
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
TIMER B CONTROL REGISTER (TBCON)
Timer B Control Register (TBCON) D0H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer B input clock selection bit: 00 = fxx/1 01 = fxx/2 10 = fxx/4 11 = fxx/8 Timer B interrupt time selection bit: 00 = Elapsed time for low data value 01 = Elapsed time for high data value 10 = Elapsed time for low and high data value 11 = Invaild setting
Timer B output flip-flop control bit: 0 = T-FF is low 1 = T-FF is high Timer B mode selection bit: 0 = One-shot mode 1 = Repeating mode Timer B start/stop bit: 0 = Stop timer B 1 = Start timer B
Timer B interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt
Figure 11-4. Timer B Control Register (TBCON)
Timer B Data High-Byte Register (TBDATAH) D1H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Reset Value: FFh Timer B Data Low-Byte Register (TBDATAL) D2H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Reset Value: FFh
Figure 11-5. Timer B Data Registers (TBDATAH, TBDATAL)
11-6
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
TIMER B PULSE WIDTH CALCULATIONS
sv~ opno sv~
To generate the above repeated waveform consisted of low period time, tLOW , and high period time, tHIGH. When T-FF = 0, tLOW = (TBDATAL + 1) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock. tHIGH = (TBDATAH + 1) x 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock. When T-FF = 1, tLOW = (TBDATAH + 1) x 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock. tHIGH = (TBDATAL + 1) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.
To make tLOW = 24 us and tHIGH = 15 us. fOSC = 4 MHz, fx = 4 MHz/4 = 1 MHz When T-FF = 0, tLOW = 24 us = (TBDATAL + 1) /fx = (TBDATAL + 1) x 1us, TBDATAL = 23. tHIGH = 15 us = (TBDATAH + 1) /fx = (TBDATAH + 1) x 1us, TBDATAH = 14. When T-FF = 1, tHIGH = 15 us = (TBDATAL + 1) /fx = (TBDATAL + 1) x 1us, TBDATAL = 14. tLOW = 24 us = (TBDATAH + 1) /fx = (TBDATAH + 1) x 1us, TBDATAH = 23.
11-7
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
Wo {GiGj
{TmmGdGNWN {ikh{hsGdGWXTmmo {ikh{hoGdGWWo {TmmGdGNWN {ikh{hsGdGWWo {ikh{hoGdGWXTmmo {TmmGdGNWN {ikh{hsGdGWWo {ikh{hoGdGWWo {TmmGdGNXN {ikh{hsGdGWWo {ikh{hoGdGWWo Wo {GiGj
o
s
s
o
XWWo
YWWo
{TmmGdGNXN {ikh{hsGdGklo {ikh{hoGdGXlo {TmmGdGNWN {ikh{hsGdGklo {ikh{hoGdGXlo {TmmGdGNXN {ikh{hsGdG^lo {ikh{hoGdG^lo {TmmGdGNWN {ikh{hsGdG^lo {ikh{hoGdG^lo
lWo YWo
lWo YWo _Wo
_Wo
_Wo
_Wo
Figure 11-6. Timer B Output Flip-Flop Waveforms in Repeat Mode
11-8
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
PROGRAMMING TIP -- To generate 38 kHz, 1/3duty signal through P2.4
This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are:
8.795 s
17.59 s 37.9 kHz 1/3 Duty
-- Timer B is used in repeat mode -- Oscillation frequency is 4 MHz (0.25 s) -- TBDATAL = 8.795 s/0.25 s = 35.18, TBDATAH = 17.59 s/0.25 s = 70.36 -- Set P2.4 to TBPWM mode. ORG DI
* * *
0100H
; Reset address
START
LD LD LD
TBDATAH,#(70-1) TBDATAL,#(35-1) TBCON,#00100111B
LD
P2CONH,#03H
; ; ; ; ; ; ; ; ; ;
Set 17.5 s Set 8.75 s Clock Source fxx Disable Timer B interrupt. Select repeat mode for Timer B. Start Timer B operation. Set Timer B Output flip-flop (T-FF) high. Set P2.4 to TBPWM mode. This command generates 38 kHz, 1/3 duty pulse signal through P2.4.
* * *
11-9
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
PROGRAMMING TIP -- To generate a one pulse signal through P2.4
This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and TBDATAH and TBDATAL to make a 40s width pulse. The program parameters are:
[WG
-- Timer B is used in one shot mode -- Oscillation frequency is 4 MHz (1 clock = 0.25 s) -- TBDATAH = 40 s / 0.25 s = 160, TBDATAL = 1 -- Set P2.4 to TBPWM mode ORG DI
* * *
0100H
; Reset address
START
LD LD LD
TBDATAH,# (160-1) TBDATAL,# 1 TBCON,#00010001B
LD
* *
P2CONH, #03H
; ; ; ; ; ; ; ;
Set 40 s Set any value except 00H Clock Source fOSC Disable Timer B interrupt. Select one shot mode for Timer B. Stop Timer B operation. Set Timer B output flip-flop (T-FF) high Set P2.4 to TBPWM mode.
Pulse_out:
LD
* * *
TBCON,#00010101B
; ; ; ;
Start Timer B operation to make the pulse at this point. After the instruction is executed, 0.75 s is required before the falling edge of the pulse starts.
11-10
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
8-BIT TIMER C (0/1)
OVERVIEW The 8-bit timer C (0/1) is an 8-bit general-purpose timer/counter. Timer C (0/1) has two operating modes, you can select one of them using the appropriate TCCON0, and TCCON1 setting: -- Interval timer mode (Toggle output at TCOUT0, TCOUT1 pin) -- PWM mode (TCOUT0, TCOUT1) Timer C (0/1) has the following functional components: -- Clock frequency divider with multiplexer -- 8-bit counter, 8-bit comparator, and 8-bit reference data register (TCDATA0, TCDATA1) -- PWM or match output (TCOUT0, TCOUT1) -- Timer C (0) match/overflow interrupt (IRQ2, vector BCH) generation -- Timer C (1) match/overflow interrupt (IRQ2, vector BEH) generation -- Timer C (0) control register, TCCON0 (set 1, bank1, F2H, read/write) -- Timer C (1) control register, TCCON1 (set 1, bank1, F3H, read/write)
11-11
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
TIMER C (0/1) CONTROL REGISTER (TCCON0, TCCON1)
Timer C Control Register (TCCON0) F2H, Set 1, Bank 1, R/W , Reset: 00H (TCCON1) F3H, Set 1, Bank 1, R/W , Reset: 00H MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 =
C 3-bits prescaler bits: Non devided Devided by 2 Devided by 3 Devided by 4 Devided by 5 Devided by 6 Devided by 7 Devided by 8
Timer C pending bit: 0 = No interrupt pending 1 = interrupt pending Timer C interrupt enable bit: 0 = Disable interrupt 1 = Enable interrrupt Timer C mode selection bit: 0 = Fx/1 & PW M mode 1 = Fx/64 & interval mode
Timer C counter clear bit: 0 = No effect 1 = Clear the timer A counter (when write) NOTE: W hen the counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically.
Figure 11-7. Timer C (0/1) Control Register (TCCON0, TCCON1)
11-12
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
BLOCK DIAGRAM
TCCON.1 TCCON.2 TCCON.6-.4 Overflow Data Bus 8 fxx/1 fxx/64 M U X 3-bit Prescaler 8-bit Up-Counter (Read Only) Clear Pending TCCON.0
TCINT
TCCON.3
TCCON.1 8-bit Comparator Match Pending TCCON.0 Timer C Buffer Reg TCCON.2
TCINT
TCOUT
Timer C Data Register (Read/Write) 8 Data Bus NOTES: 1. When PWM mode, match signal cannot clear counter.
Figure 11-8. Timer C (0/1) Functional Block Diagram
11-13
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
PROGRAMMING TIP -- Using the Timer A
ORG VECTOR VECTOR ORG INITIAL: LD LD LD LD LD LD LD SYM,#00h IMR,#00000001b SPH,#00000000b SPL,#0FFh BTCON,#10100011b TADATA,#80h TACON,#01001010b 0000h 0B8h,TAMC_INT 0BAh,TAOV_INT 0100h
; Disable Global/Fast interrupt SYM ; Enable IRQ0 interrupt ; Set stack area ; Disable watch-dog
; Match interrupt enable ; 3.30 ms duration (10 MHz x'tal)
EI MAIN:
* *
MAIN ROUTINE
* *
JR TAMC_INT:
* *
T,MAIN
Interrupt service routine
* *
IRET TAOV_INT:
*
Interrupt service routine
* *
IRET .END
11-14
S3C84BB/F84BB
8-BIT TIMER A/B/C(0/1)
PROGRAMMING TIP -- Using the Timer B
ORG VECTOR ORG INITIAL: LD LD LD LD LD LD LD LD LD SYM,#00h IMR,#00000010b SPH,#00000000b SPL,#0FFh BTCON,#10100011b P2CONH,#00000011b TBDATAH,#80h TBDATAL,#80h TBCON,#11101110b ; Disable Global/Fast interrupt ; Enable IRQ1 interrupt ; Set stack area ; Disable Watch-dog ; Enable TBPWM output 0000h 0C8h,TBUN_INT 0100h
; Enable interrupt, repeating, fxx/8 ; Duration 206 s (10 MHz x'tal)
EI MAIN:
* * *
MAIN ROUTINE
* * *
JR TBUN_INT:
* * *
T, MAIN
Interrupt service routine
* * *
IRET .END
11-15
8-BIT TIMER A/B/C(0/1)
S3C84BB/F84BB
PROGRAMMING TIP -- Using the Timer C(0)
ORG VECTOR ORG INITIAL: LD LD LD LD LD LD LD LD SYM,#00h IMR,#00000100b SPH,#00000000b SPL,#11111111b BTCON,#10100011b P3CONH,#00110000b TCDATA0,#80h TCCON0,#00001110b ; Disable Global/Fast interrupt ; Enable IRQ2 interrupt ; Set stack area ; Disable Watch-dog, high speed ; Enable TCOUT0 output 0000h 0BCh, TCUN_INT 0100h
; non-divide, interval, Enable interrupt ; Duration 0.825ms (10 MHz x'tal)
EI MAIN:
* * *
MAIN ROUTINE
* * *
JR TCUN_INT:
* * *
T, MAIN
Interrupt service routine
* * *
IRET .END
11-16
S3C84BB/F84BB
16-BIT TIMER 1(0/1)
16-BIT TIMER 1(0/1)
OVERVIEW
The S3C84BB/F84BB has two 16-bit timer/counters. The 16-bit timer 1(0/1) is a 16-bit general-purpose timer/counter. Timer 1(0/1) has three operating modes, one of which you select using the appropriate T1CON0, T1CON1 setting is: -- Interval timer mode (Toggle output at T1OUT0, T1OUT1 pin) -- Capture input mode with a rising or falling edge trigger at the T1CAP0, T1CAP1 pin -- PWM mode (T1PWM0, T1PWM1); PWM output shares their output port with T1OUT0, T1OUT1 pin Timer 1(0/1) has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer -- External clock input pin (T1CK0, T1CK1) -- A 16-bit counter (T1CNTH0/L0, T1CNTH1/L1), 16-bit comparator, and two 16-bit reference data register (T1DATAH0/L0, T1DATAH1/L1) -- I/O pins for capture input (T1CAP0, T1CAP1), or match output (T1OUT0, T1OUT1) -- Timer 1(0) overflow interrupt (IRQ3, vector C2H) and match/capture interrupt (IRQ3, vector C0H) generation -- Timer 1(1) overflow interrupt (IRQ3, vector C6H) and match/capture interrupt (IRQ3, vector C4H) generation -- Timer 1(0) control register, T1CON0 (set 1, EAH, Bank 1, read/write) -- Timer 1(1) control register, T1CON1 (set 1, EBH, Bank 1, read/write)
12-1
16-BIT TIMER 1(0/1)
S3C84BB/F84BB
FUNCTION DESCRIPTION Timer 1 (0/1) Interrupts (IRQ3, Vectors C6H, C4H, C2H and C0H) The timer 1(0) module can generate two interrupts, the timer 1(0) overflow interrupt (T1OVF0), and the timer 1(0) match/capture interrupt (T1INT0). T1OVF0 is interrupt level IRQ3, vector C2H. T1INT0 also belongs to interrupt level IRQ3, but is assigned the separate vector address, C0H. A timer 1(0) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A timer 1(0) match/capture interrupt, T1INT0 pending condition is also cleared by hardware when it has been serviced. The timer 1(1) module can generate two interrupts, the timer 1(1) overflow interrupt (T1OVF1), and the timer 1(1) match/capture interrupt (T1INT1). T1OVF1 is interrupt level IRQ3, vector C6H. T1INT1 also belongs to interrupt level IRQ3, but is assigned the separate vector address, C4H. A timer 1(1) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A timer 1(1) match/capture interrupt, T1INT1 pending condition is also cleared by hardware when it has been serviced. Interval Mode (match) The timer 1(0) module can generate an interrupt: the timer 1(0) match interrupt (T1INT0). T1INT0 belongs to interrupt level IRQ3, and is assigned the separate vector address, C0H. In interval timer mode, a match signal is generated and T1OUT0 is toggled when the counter value is identical to the value written to the T1 reference data register, T1DATAH0/L0. The match signal generates a timer 1(0) match interrupt (T1INT0, vector C0H) and clears the counter. The timer 1(1) module can generate an interrupt: the timer 1(1) match interrupt (T1INT1). T1INT1 belongs to interrupt level IRQ3, and is assigned the separate vector address, C4H. In interval timer mode, a match signal is generated and T1OUT1 is toggled when the counter value is identical to the value written to the T1 reference data register, T1DATAH1/L1. The match signal generates a timer 1(1) match interrupt (T1INT1, vector C4H) and clears the counter. Capture Mode In capture mode for Timer 1(0), a signal edge that is detected at the T1CAP0 pin opens a gate and loads the current counter value into the T1 data register (T1DATAH0/L0 for rising edge, or falling edge). You can select rising or falling edges to trigger this operation. Timer 1(0) also gives you capture input source, the signal edge at the T1CAP0 pin. You select the capture input by setting the capture input selection bit in the port 3 control register, P3CONL, (set 1 bank 0, F5H). Both kinds of timer 1(0) interrupts (T1OVF0, T1INT0) can be used in capture mode, the timer 1(0) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(0) capture interrupt is generated whenever the counter value is loaded into the T1 data register (T1DATAH0/L0). By reading the captured data value in T1DATAH0/L0, and assuming a specific value for the timer 1(0) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP0 pin. In capture mode for Timer 1(1), a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the T1 data register (T1DATAH1/L1 for rising edge, or falling edge). You can select rising or falling edges to trigger this operation. Timer 1(1) also gives you capture input source, the signal edge at the T1CAP1 pin. You select the capture input by setting the capture input selection bit in the port 3 control register, P3CONL, (set 1 bank 0, F5H). Both kinds of timer 1(1) interrupts (T1OVF1, T1INT1) can be used in capture mode, the timer 1(1) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(1) capture interrupt is generated whenever the counter value is loaded into the T1 data register. By reading the captured data value in T1DATAH1/L1, and assuming a specific value for the timer 1(1) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP1 pin.
12-2
S3C84BB/F84BB
16-BIT TIMER 1(0/1)
PWM Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1OUT0, T1OUT1 pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1(0/1) data register. In PWM mode, however, the match signal does not clear the counter but can generate a match interrupt. The counter runs continuously, overflowing at FFFFH, and then continuous increasing from 0000H. Whenever an overflow is occurred, an overflow (OVF0,1) interrupt can be generated. Although you can use the match or the overflow interrupt in the PWM mode, these interrupts are not typically used in PWM-type applications. Instead, the pulse at the T1OUT0, T1OUT1 pin is held to low level as long as the reference data value is less than or equal to() the counter value and then the pulse is held to high level for as long as the data value is greater than(>) the counter value. One pulse width is equal to tCLK . TIMER 1(0/1) CONTROL REGISTER (T1CON0, T1CON1) You use the timer 1(0/1) control register, T1CON0, T1CON1, to -- Select the timer 1(0/1) operating mode (interval timer, capture mode, or PWM mode) -- Select the timer 1(0/1) input clock frequency -- Clear the timer 1(0/1) counter, T1CNTH0/L0, T1CNTH1/L1 -- Enable the timer 1(0/1) overflow interrupt -- Enable the timer 1(0/1) match/capture interrupt T1CON0 is located in set 1 and Bank 1 at address EAH, and is read/write addressable using Register addressing mode. T1CON1 is located in set 1 and Bank 1 at address EBH, and is read/write addressable using Register addressing mode. A reset clears T1CON0, T1CON1 to `00H'. This sets timer 1(0/1) to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 1(0/1) interrupts. To disable the counter operation, please set T1CON(0/1).7-.5 to 111B. You can clear the timer 1(0/1) counter at any time during normal operation by writing a "1" to T1CON(0/1).3. To generate the exact time interval, you should write "1" to T1CON(0/1).2 and clear appropriate pending bits of the TINTPND register. To detect a match/capture or overflow interrupt pending condition when T1INT0, T1INT1 or T1OVF0, T1OVF1 is disabled, the application program should poll the pending bit TINTPND register, bank 0, E9H. When a "1" is detected, a timer 1(0/1) match/capture or overflow interrupt is pending. When the sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the interrupt pending bit. If interrupts (match/capture or overflow) are enabled, the pending bit is cleared automatically by hardware.
12-3
16-BIT TIMER 1(0/1)
S3C84BB/F84BB
Timer 1 Control Register (T1CON0) EAH, Set 1, Bank 1, R/W (T1CON1) EBH, Set 1, Bank 1, R/W
MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Timer 1 clock source selection bit: 000 = fxx/1024 001 = fxx 010 = fxx/256 011 = External clock(T1CK) falling edge 100 = fxx/64 101 = External clock(T1CK) rising edge 110 = fxx/8 111 = Counter stop
Timer 1 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrrupt Timer 1 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrrupt Timer 1 counter clear bit: 0 = No effect 1 = Clear counter (Auto-clear bit)
Timer 1 operating mode selection bit: 00 = Interval mode 01 = Capture mode (capture on rising edge, OVF can occur) 10 = Capture mode (capture on falling edge, OVF can occur) 11 = PWM mode (OVF and T1INT can occur)
NOTE: Interrupt pending bits are located in TINTPND register.
Figure 12-1. Timer 1(0/1) Control Register (T1CON0, T1CON1)
12-4
S3C84BB/F84BB
16-BIT TIMER 1(0/1)
Timer A,1 Pending Register (TINTPND) E9H, Set 1, Bank 0, R/W
MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Not used
Timer A match/capture interrupt pending bit: 0 = No interrupt pending 1 = Interrrupt pending Timer A overflow interrupt pending bit: 0 = No interrupt pending 1 = Interrupt pending Timer 1(0) match/capture interrupt pending bit: 0 = No interrupt pending 1 = Interrupt pending
Timer 1(1) overflow interrupt pendig bit: 0 = No interrupt pending 1 = Interrupt pending Timer 1(1) match/capture interrupt pending bit: 0 = No interrupt pending 1 = Interrupt pending
Timer 1(0) overflow interrupt pending bit: 0 = No interrupt pending 1 = Interrupt pending
uaGGIWIGGGIjGGGGI
Figure 12-2. Timer A and Timer 1(0/1) Pending Register (TINTPND)
12-5
16-BIT TIMER 1(0/1)
S3C84BB/F84BB
BLOCK DIAGRAM
T1CON.7-.5 T1CON.0 fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 T1CK VSS 16-bit Comparator M U X Match M U X Overflow Data Bus 8 M U X 16-bit Up-Counter (Read Only) Clear Pending TINTPND T1OVF
T1CON.2
T1CON.1 Pending TINTPND
T1INT
T1CAP
16-bit Timer Buffer
T1OUT T1PWM
T1CON.4.3 16-bit Timer Data Register (T1DATAH/L) 8 Data Bus NOTES: 1. When PWM mode, match signal cannot clear counter. 2. Pending bit is located at TINTPND register.
T1CON.4.3 PG output signal
Figure 12-3. Timer 1(0/1) Functional Block Diagram
12-6
S3C84BB/F84BB
16-BIT TIMER 1(0/1)
PROGRAMMING TIP -- Using the Timer 1(0)
ORG VECTOR ORG INITIAL: LD LD LD LD LD SB1 LDW LD SB0 EI MAIN:
* * *
0000h 0E4h,T1MC_INT 0100h
SYM,#00h IMR,#00001000b SPH,#00000000b SPL,#11111111b BTCON,#10100011b
; Disable Global/Fast interrupt ; Enable IRQ3 interrupt ; Set stack area ; Disable Watch-dog
T1DATAH0,#0F0h T1CON0,#01000110b
; fxx/256, interval, clear counter, Enable interrupt ; Duration 6.17ms (10 MHz x'tal)
MAIN ROUTINE
* * *
JR T1MC_INT:
* * *
T,MAIN
Interrupt service routine
* * *
IRET .END
12-7
16-BIT TIMER 1(0/1)
S3C84BB/F84BB
NOTES
12-8
S3C84BB/F84BB
SERIAL I/O PORT
SERIAL I/O PORT
OVERVIEW
Serial I/O module, SIO can interface with various types of external devices that require serial data transfer. SIO has the following functional components: -- SIO data receive/transmit interrupt (IRQ4, vector CAH) generation -- 8-bit control register, SIOCON (set 1, bank 1, E1H, read/write) -- Clock selection logic -- 8-bit data buffer, SIODATA -- 8-bit prescaler (SIOPS), (set 1, bank 1, F4H, read/write) -- 3-bit serial clock counter -- Serial data I/O pins (P2.0-P2.1, SO, SI) -- External clock input/output pin (P2.2, SCK) The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO modules, follow these basic steps: 1. Configure P2.1, P2.0 and P2.2 to alternative function (SI, SO, SCK) for interfacing SIO module by setting the P2CONL register to appropriately value. 2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. 3. For interrupt generation, set the serial I/O interrupt enable bit, SIOCON.1 to "1". 4. To transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, then the shift operation starts. 5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) is set to "1" and an SIO interrupt request is generated.
13-1
SERIAL I/O PORT
S3C84BB/F84BB)
SIO CONTROL REGISTER (SIOCON) The control register for the serial I/O interface module, SIOCON, is located in set 1, bank 1 at address E1H. It has the control settings for SIO module. -- Clock source selection (internal or external) for shift clock -- Interrupt enable -- Edge selection for shift operation -- Clear 3-bit counter and start shift operation -- Shift operation (transmit) enable -- Mode selection (transmit/receive or receive-only) -- Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to '00H'. This configures the corresponding module with an internal clock source, P.S clock at the SCK, selects receive-only operating mode, the data shift operation and the interrupt are disabled, and the data direction is selected to MSB-first. So, if you want to use SIO module, you must write appropriate value to SIOCON.
Serial I/O Module Control Registers (SIOCON) E1H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SIO Shift clock selection bit: 0 = Internal clock (P.S clock) 1 = External Clock (SCK)
SIO interrupt pending bit: 0 = No interrupt pending 0 = Clear pending condition (when write) 1 = Interrupt is pending SIO interrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shifter and clock counter SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting
Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selection bit: 0 = Receive-only mode 1 = Transmit/receive mode Shift clock edge selection bit: 0 = TX at falling edeges, RX at rising edges 1 = TX at rising edeges, RX at falling edges
Figure 13-1. SIO Module Control Register (SIOCON)
13-2
S3C84BB/F84BB
SERIAL I/O PORT
SIO PRESCALER REGISTER (SIOPS) The control register for the serial I/O interface module, SIOPS, is located in set 1, bank 1, at address F4H. The value stored in the SIO prescaler registers, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx)/[(SIOPS value + 1) x 2] or SCK input clock
SIO Pre-Scaler Register (SIOPS) F4H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
SIOPS Data Value Baud rate = Input clock (fxx)/[(SIOPS + 1) x 2] or SCLK input clock Figure 13-2. SIO Prescaler Register (SIOPS) BLOCK DIAGRAM
CLK
3-Bit Counter Clear SIOCON.3 SIOCON.4 (Shift Clock Edge Select)
SIOCON.0 Pending
SIO INT IRQ4
SIOCON.7 (Shift Clock Source Select) SCK(P2.2) M SIOPS 8-bit P.S. U 1/2 X
SIOCON.1 (Interrupt Enable) SIOCON.2 (Shift Enable)
SIOCON.5 (Mode Select)
fxx
CLK 8-Bit SIO Shift Buffer (SIODATA) SO (P2.0) 8 SIOCON.6 (LSB/MSB First Mode Select)
Prescaled Value = 1/(SIOPS +1)
SI (P2.1) Data BUS
Figure 13-3. SIO Functional Block Diagram
13-3
SERIAL I/O PORT
S3C84BB/F84BB)
SERIAL I/O TIMING DIAGRAMS
Shift Clock
SI (Data Input)
D7
D6
D5
D4
D3
D2
D1
D0
SO (Data Output)
D7
D6
D5
D4
D3
D2
D1
D0
IRQ4 SET SIOCON.3
Transmit Complete
Figure 13-4. SIO Timing in Transmit/Receive Mode (Tx at falling edge, SIOCON.4=0)
Shift Clock
SI (Data Input)
D7
D6
D5
D4
D3
D2
D1
D0
SO (Data Output)
D7
D6
D5
D4
D3
D2
D1
D0
IRQ4 SET SIOCON.3
Transmit Complete
Figure 13-5. SIO Timing in Transmit/Receive Mode (Tx at rising edge, SIOCON.4=1)
13-4
S3C84BB/F84BB
SERIAL I/O PORT
Shift Clock
SI
D7
D6
D5
D4
D3
D2
D1
D0
High Impedance SO
IRQ4 SET SIOCON.3
Transmit Complete
Figure 13-6. SIO Timing in Receive-Only Mode (Rising edge start)
PROGRAMMING TIP -- Use Internal Clock to Transmit and Receive Serial Data
1. The method that uses interrupt is used.
* *
DI LD
P2CONL #03H
; Disable All interrupts ; P2.2-P2.0 are selected to alternative function for ; SI, SO, SCK, respectively
SB1 LD LD LD SB0
SIODATA, TDATA SIOPS, #90H SIOCON, #2EH
; ; ; ; ; ; ;
Load data to SIO buffer Baud rate = input clock(fxx)/[(144 + 1) x 2] Internal clock, MSB first, transmit/receive mode Select Tx falling edges to start shift operation Clear 3-bit counter and start shifting Enable shifter and clock counter Enable SIO interrupt and clear pending
EI
* * *
SIOINT
PUSH SRP0 SB1 LD OR AND POP IRET
RP0 #RDATA R0,SIODATA SIOCON,#08H SIOCON,#11111110b RP0
; ; ; Load received data to general register ; SIO restart ; Clear interrupt pending bit
13-5
SERIAL I/O PORT
S3C84BB/F84BB)
PROGRAMMING TIP -- Use Internal Clock to Transfer and Receive Serial Data (Continued)
2. The method that uses software pending check is used.
* * *
DI SB1 LD LD LD
; Disable All interrupts
SIODATA, TDATA SIOPS, #90H SIOCON, #2CH
; ; ; ; ; ;
Load data to SIO buffer Baud rate = input clock(fxx)/[(144 + 1) x 2] Internal clock, MSB first, transmit/receive mode Select falling edges to start shift operation clear 3-bit counter and start shifting Disable SIO interrupt and pending clear
EI SIOtest: LD BTJRF NOP AND LD
* * *
R6,SIOCON SIOtest,R6.0 SIOCON,#0FEH RDATA,SIODATA
; To check whether transmit and receive is finished ; Check pending bit ; Pending clear by software ; Load received data to RDATA
SB0
* * *
13-6
S3C84BB/F84BB
UART(0/1)
14
OVERVIEW
UART(0/1)
The UART block has a full-duplex serial port with programmable operating modes: There is one synchronous mode and three UART (Universal Asynchronous Receiver/Transmitter) modes: -- Serial I/O with baud rate of fxx/(16 x (BRDATA+1)) -- 8-bit UART mode; variable baud rate -- 9-bit UART mode; fxx/16 -- 9-bit UART mode, variable baud rate UART receive and transmit buffers are both accessed via the data register, UDATA0, is set 1, bank 1 at address E2H, UDATA1, is set 1, bank 1 at address FAH. Writing to the UART data register loads the transmit buffer; reading the UART data register accesses a physically separate receive buffer. When accessing a receive data buffer (shift register), reception of the next byte can begin before the previously received byte has been read from the receive register. However, if the first byte has not been read by the time the next byte has been completely received, the first data byte will be lost. In all operating modes, transmission is started when any instruction (usually a write operation) uses the UDATA0, UDATA1 register as its destination address. In mode 0, serial data reception starts when the receive interrupt pending bit (UARTPND.1, UARTPND.3) is "0" and the receive enable bit (UARTCON0.4, UARTCON1.4) is "1". In mode 1, 2, and 3, reception starts whenever an incoming start bit ("0") is received and the receive enable bit (UARTCON0.4, UARTCON1.4) is set to "1". PROGRAMMING PROCEDURE To program the UART0 modules, follow these basic steps: 1. Configure P5.3 and P5.2 to alternative function RxD0, TxD0 for UART0 module by setting the P5CONL register to appropriatly value. 2. Load an 8-bit value to the UARTCON0 control register to properly configure the UART0 I/O module. 3. For interrupt generation, set the UART0 interrupt enable bit (UARTCON0.1 or UARTCON0.0) to "1". 4. When you transmit data to the UART0 buffer, writing data to UDATA0, the shift operation starts. 5. When the shift operation (transmit/receive) is completed, UART0 pending bit (UARTPND.1 or UARTPND.0) is set to "1" and an UART0 interrupt request is generated.
14-1
UART(0/1)
S3C84BB/F84BB
UART CONTROL REGISTER (UARTCON0, UARTCON1) The control register for the UART is called UARTCON0 in set 1, bank 1 at address E3H, UARTCON1 in set 1, bank 1 at address FBH. It has the following control functions: -- -- -- -- -- Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable/disable control 9th data bit location for transmit and receive operations (modes 2 and 3 only) UART transmit and receive interrupt control
A reset clears the UARTCON0, UARTCON1 value to "00H". So, if you want to use UART0, or UART1 module, you must write appropriate value to UARTCON0, UARTCON1.
UART Control Register (UARTCON0) E3H, Set 1, Bank 1, R/W (UARTCON1) FBH, Set 1, Bank 1, R/W MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSB
Operating mode and baud rate selection bits (see table below) Multiprocessor communication(1) enable bit (for modes 2 and 3 only): 0 = Disable 1 = Enable Serial data receive enable bit: 0 = Disable 1 = Enable
Transmit interrupt enable bit: 0 = Disable 1 = Enable Received interrupt enable bit: 0 = Disable 1 = Enable Location of the 9th data bit that was received in UART mode 2 or 3 ("0" or "1")
Location of the 9th data bit to be transmitted in UART mode 2 or 3 ("0" or "1") MS1 MS0 Mode Description(2) Baud Rate 0 0 1 1 0 1 0 1 0 1 2 3 Shift register 8-bit UART 9-bit UART 9-bit UART fxx/(16 x (BRDATA + 1)) fxx/(16 x (BRDATA + 1)) fxx/16 fxx/(16 x (BRDATA + 1))
NOTES: 1. In mode 2 or 3, if the UARTCON.5 bit is set to "1" then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if UARTCON.5 = "1" then the receive interrut will not be activated if a valid stop bit was not received. In mode 0, the UARTCON.5 bit should be "0" 2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
Figure 14-1. UART Control Register (UARTCON0, UARTCON1)
14-2
S3C84BB/F84BB
UART(0/1)
UART INTERRUPT PENDING REGISTER (UARTPND) The UART interrupt pending register, UARTPND is located in set 1, bank 1 at address E5H, it contains the UART0 data transmit interrupt pending bit (UARTPND.0), the receive interrupt pending bit (UARTPND.1), the UART1 data transmit interrupt pending bit (UARTPND.2), and the receive interrupt pending bit (UARTPND.3). In mode 0, the receive interrupt pending flag UARTPND.1, UARTPND.3 is set to "1" when the 8th receive data bit has been shifted. In mode 1, 2, and 3, the UARTPND.1, UARTPND.3 bit is set to "1" at the halfway point of the stop bit's shift time. When the CPU has acknowledged the receive interrupt pending condition, the UARTPND.1, UARTPND.3 flag must then be cleared by software in the interrupt service routine. In mode 0, the transmit interrupt pending flag UARTPND.0, UARTPND.2 is set to "1" when the 8th transmit data bit has been shifted. In mode 1, 2, or 3, the UARTPND.0, UARTPND.2 bit is set at the start of the stop bit. When the CPU has acknowledged the transmit interrupt pending condition, the UARTPND.0, UARTPND.2 flag must then be cleared by software in the interrupt service routine.
UART Pending Register (UARTPND) E5H, Set 1, Bank 1, R/W MSB RIP1 TIP1 RIP0 TIP0 LSB
Not used UART1 receive interrupt pending flag: 0 = Not pending 0 = Clear pending bit (when write) 1 = Interrupt pending
UART0 transmit interrupt pending flag: 0 = Not pending 0 = Clear pending bit (when write) 1 = Interrupt pending
UART0 receive interrupt pending flag: 0 = Not pending UART1 transmit interrupt pending flag: 0 = Clear pending bit (when write) 0 = Not pending 1 = Interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt pending In order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. 2. To avoid errors, we recommend using load instruction (except for LDB), when manipulating UARTPND values.
NOTES: 1.
Figure 14-2. UART Interrupt Pending Register (UARTPND)
14-3
UART(0/1)
S3C84BB/F84BB
UART DATA REGISTER (UDATA0, UDATA1)
UART Data Register (UDATA0) E2H, Set 1, Bank 1, R/W (UDATA1) FAH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Transmit or receive data
Figure 14-3. UART Data Register (UDATA0, UDATA1)
UART BAUD RATE DATA REGISTER (BRDATA0, BRDATA1) The value stored in the UART0 baud rate register, BRDATA0, lets you determine the UART0 clock rate (baud rate). The value stored in the UART1 baud rate register, BRDATA1, lets you determine the UART1 clock rate (baud rate).
UART Baud Rate Data Register (BRDATA0) E4H, Set 1, Bank 1, R/W (BRDATA1) FCH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Baud rate data
Figure 14-4. UART Baud Rate Data Register (BRDATA0, BRDATA1) BAUD RATE CALCULATIONS (UART0) Mode 0 Baud Rate Calculation In mode 0, the baud rate is determined by the UART0 baud rate data register, BRDATA0 in set1, bank 1 at address E4H. Mode 0 baud rate = fxx/(16 x (BRDATA0 + 1)) Mode 2 Baud Rate Calculation The baud rate in mode 2 is fixed at the fOSC clock frequency divided by 16: Mode 2 baud rate = fxx/16 Modes 1 and 3 Baud Rate Calculation In modes 1 and 3, the baud rate is determined by the UART0 baud rate data register, BRDATA0 in set 1, bank 1 at address E4H. Mode 1 and 3 baud rate = fxx/(16 x (BRDATA0 + 1))
14-4
S3C84BB/F84BB
UART(0/1)
Table 14-1. Commonly Used Baud Rates Generated by BRDATA0, BRDATA1 Mode Mode 2 Mode 0 Mode 1 Mode 3 Baud Rate 0.5 MHz 230,400 Hz 115,200 Hz 57,600 Hz 38,400 Hz 19,200 Hz 9,600 Hz 4,800 Hz 62,500 Hz 9,615 Hz 38,461 Hz 12,500 Hz 19,230 Hz 9,615 Hz Oscillation Clock 8 MHz 11.0592 MHz 11.0592 MHz 11.0592 MHz 11.0592 MHz 11.0592 MHz 11.0592 MHz 11.0592 MHz 10 MHz 10 MHz 8 MHz 8 MHz 4 MHz 4 MHz BRDATA0, BRDATA1 Decimal x 02 05 11 17 35 71 143 09 64 12 39 12 25 Hexdecimal x 02H 05H 0BH 11H 23H 47H 8FH 09H 40H 0CH 27H 0CH 19H
14-5
UART(0/1)
S3C84BB/F84BB
BLOCK DIAGRAM
SAM8 Internal Data Bus TB8 MS0 MS1 BRDATA S D Q CLK UARTDATA CLK Zero Detector MS0 MS1 RxD0 (P5.3) RxD1 (P5.1)
fxx
Baud Rate Generator
Write to UARTDATA
Start
Shift
Tx Control
Tx Clock TIP
TxD0 (P5.2) TxD1 (P5.0)
EN Send TxD0 (P5.2) TxD1 (P5.0)
IRQ7 Interrupt
TIE RIE
Shift Clock
Rx Clock RE RIE 1-to-0 Transition Detector Start
RIP
Receive Shift Shift Value
Rx Control
Bit Detector
MS0 MS1
Shift Register
UARTDATA RxD0 (P5.3) RxD1 (P5.1) SAM8 Internal Data Bus
Figure 14-5. UART Functional Block Diagram
14-6
S3C84BB/F84BB
UART(0/1)
UART0 MODE 0 FUNCTION DESCRIPTION In mode 0, UART0 is input and output through the RxD0 (P5.3) pin and TxD0 (P5.2) pin outputs the shift clock. Data is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first. Mode 0 Transmit Procedure 1. Select mode 0 by setting UARTCON0.6 and .7 to "00B". 2. Write transmission data to the shift register UDATA0 (E2H, set 1, bank 1) to start the transmission operation. Mode 0 Receive Procedure 1. Select mode 0 by setting UATCON0.6 and .7 to "00B". 2. Clear the receive interrupt pending bit (UARTPND.1) by writing a "0" to UARTPND.1. 3. Set the UART0 receive enable bit (UARTCON0.4) to "1". 4. The shift clock will now be output to the TxD0 (P5.2) pin and will read the data at the RxD0 (P5.3) pin. A UART0 receive interrupt (IRQ7, vector F0H) occurs when UARTCON0.1 is set to "1".
Write to Shift Register (UDATA) Shift
RxD (Data Out) TxD (Shift Clock)
D0
D1
D2
D3
D4
D5
D6
D7
TIP Write to UARTPND (Clear RIP and set RE) RIP
RE Receive D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8
Shift
RxD (Data In)
TxD (Shift Clock)
Figure 14-6. Timing Diagram for UART Mode 0 Operation
Transmit
14-7
UART(0/1)
S3C84BB/F84BB
UART0 MODE 1 FUNCTION DESCRIPTION In mode 1, 10-bits are transmitted through the TxD0 pin or received through the RxD0 pin. Each data frame has three components: -- Start bit ("0") -- 8 data bits (LSB first) -- Stop bit ("1") When receiving, the stop bit is written to the RB8 bit in the UARTCON0 register. The baud rate for mode 1 is variable. Mode 1 Transmit Procedure 1. Select the baud rate generated by setting BRDATA0. 2. Select mode 1 (8-bit UART0) by setting UARTCON0 bits 7 and 6 to '01B'. 3. Write transmission data to the shift register UDATA0 (E2H, set 1, bank 1). The start and stop bits are generated automatically by hardware. Mode 1 Receive Procedure 1. Select the baud rate to be generated by setting BRDATA0. 2. Select mode 1 and set the RE (Receive Enable) bit in the UARTCON0 register to "1". 3. The start bit low ("0") condition at the RxD0 (P5.3) pin will cause the UART0 module to start the serial data receive operation.
Tx Clock Write to Shift Register (UDATA) Shift TxD TIP Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Rx Clock RxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Bit Detect Sample Time Shift RIP Receive
Figure 14-7. Timing Diagram for UART Mode 1 Operation
14-8
Transmit
S3C84BB/F84BB
UART(0/1)
UART0 MODE 2 FUNCTION DESCRIPTION In mode 2, 11-bits are transmitted (through the TxD0 pin) or received (through the RxD0 pin). Each data frame has four components: -- Start bit ("0") -- 8 data bits (LSB first) -- Programmable 9th data bit -- Stop bit ("1") The 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the TB8 bit (UARTCON0.3). When receiving, the 9th data bit that is received is written to the RB8 bit (UARTCON0.2), while the stop bit is ignored. The baud rate for mode 2 is fosc/16 clock frequency. Mode 2 Transmit Procedure 1. Select mode 2 (9-bit UART0) by setting UARTCON0 bits 6 and 7 to '10B'. Also, select the 9th data bit to be transmitted by writing TB8 to "0" or "1". 2. Write transmission data to the shift register, UDATA0 (E2H, set 1, bank 1), to start the transmit operation. Mode 2 Receive Procedure 1. Select mode 2 and set the receive enable bit (RE) in the UARTCON0 register to "1". 2. The receive operation starts when the signal at the RxD pin goes to low level.
Tx Clock Write to Shift Register (UARTDATA) Shift TxD TIP Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit
Rx Clock RxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit
Bit Detect Sample Time Shift RIP Receive
Figure 14-8. Timing Diagram for UART Mode 2 Operation
Transmit
14-9
UART(0/1)
S3C84BB/F84BB
UART0 MODE 3 FUNCTION DESCRIPTION In mode 3, 11-bits are transmitted (through the TxD0) or received (through the RxD0). Mode 3 is identical to mode 2 except for baud rate, which is variable. Each data frame has four components: -- Start bit ("0") -- 8 data bits (LSB first) -- Programmable 9th data bit -- Stop bit ("1") Mode 3 Transmit Procedure 1. Select the baud rate generated by setting BRDATA0. 2. Select mode 3 operation (9-bit UART0) by setting UARTCON0 bits 6 and 7 to '11B'. Also, select the 9th data bit to be transmitted by writing UARTCON0.3 (TB8) to "0" or "1". 3. Write transmission data to the shift register, UDATA0 (E2H, set 1, bank 1), to start the transmit operation. Mode 3 Receive Procedure 1. Select the baud rate to be generated by setting BRDATA0. 2. Select mode 3 and set the RE (Receive Enable) bit in the UARTCON0 register to "1". 3. The receive operation will be started when the signal at the RxD0 pin goes to low level.
Tx Clock Write to Shift Register (UARTDATA) Shift TxD TIP Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit
Rx Clock RxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit
Bit Detect Sample Time Shift RIP Receive
Figure 14-9. Timing Diagram for UART Mode 3 Operation
14-10
Transmit
S3C84BB/F84BB
UART(0/1)
SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C8-series multiprocessor communication feature lets a "master" S3C84BB/S3F84BB send a multipleframe serial message to a "slave" device in a multi-S3C84BB/F84BB configuration. It does this without interrupting other slave devices that may be on the same serial line. This feature can be used only in UART modes 2 or 3. In these modes 2 and 3, 9 data bits are received. The 9th bit value is written to RB8 (UARTCON0.2, or UARTCON1.2). The data receive operation is concluded with a stop bit. You can program this function so that when the stop bit is received, the serial interrupt will be generated only if RB8 = "1". To enable this feature, you set the MCE bit in the UARTCON0/1 register. When the MCE bit is "1", serial data frames that are received with the 9th bit = "0" do not generate an interrupt. In this case, the 9th bit simply separates the address from the serial data. Sample Protocol for Master/Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an address byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In an address byte, the 9th bit is "1" and in a data byte, it is "0". The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed. The addressed slave then clears its MCE bit and prepares to receive incoming data bytes. The MCE bits of slaves that were not addressed remain set, and they continue operating normally while ignoring the incoming data bytes. While the MCE bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit. For mode 1 reception, if MCE is "1", the receive interrupt will be issue unless a valid stop bit is received.
14-11
UART(0/1)
S3C84BB/F84BB
Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications: 1. Set all S3C84BB/F84BB devices (masters and slaves) to UART mode 2 or 3. 2. Write the MCE bit of all the slave devices to "1". 3. The master device's transmission protocol is: -- First byte: the address identifying the target slave device (9th bit = "1") -- Next bytes: data (9th bit = "0") 4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1". The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data. The other slaves continue operating normally.
Full-Duplex Multi-S3C84BB/F84BB Interconnect
TxD RxD Master S3C84BB/F84BB
TxD RxD Slave 1 S3C84BB/F84BB
TxD RxD Slave 2 S3C84BB/F84BB
...
TxD RxD Slave n S3C84BB/F84BB
Figure 14-10. Connection Example for Multiprocessor Serial Data Communications
14-12
S3C84BB/F84BB
10-BIT A/D CONVERTER
10-BIT A/D CONVERTER
OVERVIEW
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register, ADACON (set 1, bank 1, F7H, read/write, but ADCON.3 is read only) -- Eight multiplexed analog data input pins (ADC0-ADC7) -- 10-bit A/D conversion data output register (ADDATAH, ADDATAL) -- Internal AVREF and AVSS
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at first, you must configure P7.0-P7.7 to analog input before A/D conversions because the P7.0 - P7.7 pins can be used alternatively as normal data input or analog input pins. To do this, you load the appropriate value to the P7CON.0 - P7CON.7 (for ADC0 - ADC7) register. And you write the channel selection data in the A/D converter control register ADACON to select one of the eight analog input pins (ADCn, n = 0-7) and set the conversion start or enable bit, ADACON.0. An 10-bit conversion operation can be performed for only one analog input channel at a time. The read-write ADACON register is located in set 1, bank 1 at address F7H. During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADACON.6-4) in the ADACON register. To start the A/D conversion, you should set the enable bit, ADACON.0. When a conversion is completed, ADACON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH, ADDATAL registers where it can be read. The ADC module enters an idle state. Remember to read the contents of ADDATAH and ADDATAL before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the ADC0-ADC7 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to circuit noise, will invalidate the result.
15-1
10-BIT A/D CONVERTER
S3C84BB/F84BB
A/D CONVERTER CONTROL REGISTER (ADACON) The A/D converter control register, ADACON, is located in set1, bank 1 at address F7H. ADACON is read-write addressable using 8-bit instructions only. But EOC bit, ADACON.3 is read only. ADACON has four functions: -- Bits 6-4 select an analog input pin (ADC0-ADC7). -- Bit 3 indicates the end of conversion status of the A/D conversion. -- Bits 2-1 select a conversion speed. -- Bit 0 starts the A/D conversion. Only one analog input channel can be selected at a time. You can dynamically select any one of the eight analog input pins, ADC0-ADC7 by manipulating the 3-bit value for ADACON.6-ADACON.4
A/D, D/A Converter Control Register (ADACON) F7H, Set 1, Bank 1, R/W (ADCON.3 bit is read-only) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
D/A Start or Enable bit 0 = Disable Operation 1 = Start Operation A/D Input Pin Selection bits: .6 .5.4 000 001 010 011 100 101 110 111 A/D Input Pin ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
A/D Start or Enable bit 0 = Disable Operation 1 = Start Operation Clock Selection bit: .2 .1 Conversion Clock 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/4 fxx
End-of-Conversion bit (read only): 0 = Conversion not complete 1 = Conversion complete
Figure 15-1. A/D Converter Control Register (ADACON)
15-2
S3C84BB/F84BB
10-BIT A/D CONVERTER
Conversion Data Register High Byte (ADDATAH) F8H, Set 1, Bank 1, Read only MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Conversion Data Register Low Byte (ADDATAL) F9H, Set 1, Bank 1, Read only MSB x x x x x x .1 .0 LSB
Figure 15-2. A/D Converter Data Register (ADDATAH, ADDATAL)
ADACON.4-.6 (Select one input pin of the assigned)
ADACON.2-.1
To ADACON.3 (EOC Flag)
Input Pins ADC0-ADC7 (P7.0-P7.7)
M u l t i p l e x e r
Clock Selector ADACON.0 (AD/C Enable) + ADACON.0 (A/D Conversion enable)
Analog Comparator
Successive Approximation Logic 10-bit result is loaded into A/D Conversion Data Register
10-bit D/A Converter
AVREF AVSS
Conversion Result (ADDATAH,ADDATAL)
To Data
Figure 15-3. A/D Converter Circuit Diagram
15-3
10-BIT A/D CONVERTER
S3C84BB/F84BB
INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AVSS to AVREF (usually AVREF = VDD). Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 AVREF. CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D conversion. Therefore, total of 50 clocks is required to complete a 10-bit conversion. With a 10 MHz CPU clock frequency, one clock cycle is 400 ns (4/fxx). If each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 s at 10 MHz, 1 clock time = 4/fxx
hkhjvuUWGGGGGGX j z 50 ADC Clock
lvj
hkkh{h w }
7/7/ 7
zGG XWG
_
^
]
\
[
Z
Y
X
W } k
ADDATAH (8-Bit) + ADDATAL (2-Bit) 40 Clock
Figure 15-4. A/D Converter Timing Diagram
15-4
S3C84BB/F84BB
10-BIT A/D CONVERTER
INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of AVSS and AVREF. 2. 3. Configure P7.0-P7.7 for analog input before A/D conversions. To do this, you load the appropriate value to the P7CON (for ADC0-ADC7) register. Before the conversion operation starts, you must first select one of the eight input pins (ADC0-ADC7) by writing the appropriate value to the ADACON register.
4. When conversion has been completed, (50 clocks have elapsed), the EOC, ADACON.3 flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit), then the ADC module enters an idle state. 6. The digital conversion result can now be read from the ADDATAH and ADDATAL register.
VDD Reference Voltage Input R1 AVREF C1 C2 S3C84BB/ F84BB Analog Input C3 AVSS VSS R2 ADC0-ADC7
NOTE:
The symbol "R1" signifies an offset resistor with a value of from 50 to 100 . If this resistor is omitted, the absolute accuracy will be maximum of 3LSBs. C1=10F, C2=100 to 1000pF, C3=100 to 1000pF, R1=50 to 100, R2=10 to 1K.
Figure 15-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy
15-5
10-BIT A/D CONVERTER
S3C84BB/F84BB
PROGRAMMING TIP -- Configuring A/D Converter
* * SB0 LD * * SB1 LD TM JR LD LD SB0 * * SB1 LD TM JR LD LD SB0 * *
P7CON,#11111111B
; P7.7-P7.0 A/D Input MODE
AD0_CHK:
ADACON,#00000001B ADACON,#00001000B Z, AD0_CHK AD0BUFH,ADDATAH AD0BUFL,ADDATAL
; Channel ADC0, Conversion start ; A/D conversion end ? EOC check ; No ; 8-bit Conversion data ; 2-bit Conversion data
AD3_CHK:
ADACON,#00110001B ADACON,#00001000B Z,AD3_CHK AD3BUFH,ADDATAH AD3BUFL,ADDATAL
; Channel AD3, fxx/16, Conversion start ; A/D conversion end ? EOC check ; No ; 8-bit Conversion data ; 2-bit Conversion data
15-6
S3C84BB/F84BB
8-BIT D/A CONVERTER
8-BIT D/A CONVERTER
OVERVIEW
The S3C84BB/F84BB has 8-bit Digital-to-Analog converter with R-2R structure. This DAC(Digital-to-Analog) is 8 used to generate analog voltage, VDA, with 256 steps(2 ) The function is controlled by ADACON. To enable the converter, the ADACON.7 must be set to"1". To generate analog voltage(VDA), load the appropriate value to DADATA. The level of analog voltage is determined by DADATA. -- D/A converter logic (resistor string type) -- 8-bit D/A conversion data register, DADATA (Set 1, bank1, F6H, read/write)
16-1
8-BIT D/A CONVERTER
S3C84BB/F84BB
D/A CONVERTER CONTROL REGISTER (ADACON) The Digital-to-Analog converter (DAC) control register, ADACON, is a 8-bit register located at F7H (set1, bank1). ADACON register controls to enable or disable the Digital-to-Analog converter (DAC).
A/D, D/A Converter Control Register (ADACON) F7H, Set 1, Bank 1, R/W (ADCON.3 bit is read-only) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
D/A Start or Enable bit 0 = Disable Operation 1 = Start Operation A/D Input Pin Selection bits: .6 .5.4 000 001 010 011 100 101 110 111 A/D Input Pin ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
A/D Start or Enable bit 0 = Disable Operation 1 = Start Operation Clock Selection bit: .2 .1 Conversion Clock 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/4 fxx
End-of-Conversion bit (read only): 0 = Conversion not complete 1 = Conversion complete
Figure 16-1. D/A Converter Control Register (ADACON)
D/A CONVERTER DATA REGISTER (DADATA) DADATA, is a 8-bit read and write register located at F6H (set1, bank1). The DADATA specifies the digital data to generate analog voltage. ADACON values are set to logic "0" following RESET and the value disable DAC.
Conversion Data Register Byte (DADATA) F6H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Figure 16-2. D/A Converter Data Register (DADATA) These are the values be determined by setting just one-bit of DADATA.0-DADATA.7. The other values of DAOUT can be obtained with superimposition.
16-2
S3C84BB/F84BB
8-BIT D/A CONVERTER
BLOCK DIAGRAM
kh{hGi|z
DADATA
.0
.1
.2
.3
.4
.5
.6
.7
2R
2R
2R
2R
2R
2R
2R
2R DAOUT
2R
R
R
R
R
R
R
R
ADACON.7
Figure 16-3. D/A Converter Circuit Diagram
Table 16-1. DADATA Setting to Generate Analog Voltage DADATA7 0 1 0 0 0 0 0 0 0 DADATA6 0 0 1 0 0 0 0 0 0 DADATA5 0 0 0 1 0 0 0 0 0 DADATA4 0 0 0 0 1 0 0 0 0 DADATA3 0 0 0 0 0 1 0 0 0 DADATA2 0 0 0 0 0 0 1 0 0 DADATA1 0 0 0 0 0 0 0 1 0 DADATA0 0 0 0 0 0 0 0 0 1 VDAOUT 0 VDD/2
1 2 3 4 5 6 7 8
VDD/2 VDD/2 VDD/2 VDD/2 VDD/2 VDD/2 VDD/2
16-3
8-BIT D/A CONVERTER
S3C84BB/F84BB
NOTES
16-4
S3C84BB/F84BB
PATTERN GENERATION MODULE
PATTERN GENERATION MODULE
OVERVIEW
PATTERN GENERATION FLOW You can output up to 8-bit through P0.0-P0.7 by tracing the following sequence. First of all, you have to change the PGDATA into what you want to output. And then you have to set the PGCON to enable the pattern generation module and select the triggering signal. From now, bits of PGDATA are on the P0.0-P0.7 whenever the selected triggering signal occurs.
Write pattern data to PGDATA
Triggering signal selection: PGCON.3-.0
Triggering signal generation
Data output through P0.0-P0.7
Figure 17-1. Pattern Generation Flow
17-1
PATTERN GENERATION MODULE
S3C84BB/F84BB
Pattern Generation Module Control Register (PGCON) FEH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0
Not used
PG operation mode selection bit 00 01 10 11 Timer A match signal triggering Timer B underflow signal triggering Timer 1(0) match signal triggering S/W triggering mode
Bit2: 0 = PG operation disable 1 = PG operation enable Bit3: 0 = No effect 1 = S/W trigger start (auto clear)
Figure 17-2. PG Control Register (PGCON)
PGDATA (Set 1, Bank 1, FFH) .7 .6 .5 .4 .3 .2 .1 .0
PG Buffer .7 .6 .5 .4 .3 .2 .1 .0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
S/W Timer A match signal Timer B underflow signal Timer 1(0) match signal
Figure 17-3. Pattern Generation Circuit Diagram
17-2
S3C84BB/F84BB
PATTERN GENERATION MODULE
Programming Tip -- Using the Pattern Generation
ORG ORG INITIAL: SB0 LD LD LD LD LD LD LD EI MAIN: NOP NOP SB1 LD OR SB0 NOP NOP JR .END T,MAIN SYM,#00h IMR,#01h SPH,#0h SPL,#0FFh BTCON,#10100011b CLKCON,#00011000b P0CON,#11111111b ; ; ; ; ; ; Disable Global interrupt SYM Enable IRQ0 interrupt High byte of stack pointer SPH Low byte of stack pointer SPL Disable Watch-dog Non-divided 0000h 0100h
; Enable PG output
PGDATA,#10101010b PGCON,#00001111b
; Setting pattern data ; Triggering then pattern data are output
17-3
PATTERN GENERATION MODULE
S3C84BB/F84BB
NOTES
17-4
S3C84BB/F84BB
EMBEDDED FLASH MEMORY INTERFACE
18
OVERVIEW
EMBEDDED FLASH MEMEORY INTERFACE
The S3F84BB has an on-chip flash EEPROM instead of masked ROM. The flash EEPROM is accessed by serial data format and the type of a full flash, that is, a user can program the data in a flash memory area any time you wants. The flash EEPROM Endurance is 100 cycles for Erase/Program operation. The S3F84BB's embedded 64k-byte memory has several operating features below: The S3F84BB has 6 pins used to read/write the flash memory, VDD/VSS, Reset, Test, SDAT and SCLK. The flash memory control block supports two kinds of program mode: -- Tool Program Mode -- User Program Mode Tool Program Mode The 6 pins are connected to a programming tool and programmed by Serial OTP/MTP Tools (SPW2plus single programmer, or GW-PRO2 gang programmer). The 12.5V programming power is supplied into the Vpp (Test) pin. The other modules except flash EEPROM module are at a reset state. This mode doesn't support sector erase but chips erase and two protection modes (Hard lock protection/ Read protection). User Program Mode This mode supports sector erase and two protection modes. The S3F84BB has the pumping circuit internally, therefore, 12.5V into Vpp (Test) pin is not needed. To program a flash memory in this mode several control registers will be used, refer to page 18-2. During programming/erasing flash memory, CPU will be held (30us) automatically. Two signals, SCLK, SDAT should be made in User Program Mode by using FSCLK and FSDAT bit in FMCON register (address FDh in set1, bank1) in order to program a flash memory. There are three kind functions - sector erase, programming, Option sector programming in User Program Mode. Serial Interface Protocol Format Serial interface protocol format consist of 3-byte address field and two and more byte data field. In the 1st byte of address field, 4-bits are assigned for serial interface mode, the other 4-bits are assigned for address extension. (See Figure 18-4, and 18-5) Data valid status of SCLK: High Data Invalid status of SCLK: Low START condition : SCLK = high, and SDAT = positive Edge STOP condition : SCLK = high, and SDAT = negative Edge
18-1
EMBEDDED FLASH MEMORY INTERFACE
S3C84BB/F84BB
Table 18-1. Command in User Program Mode ... Mode Bit n Program REG/ MEMB B23 0 1st Byte MODE (M1-M0) B22-B21 11b ADDRESS (A19-A16) B20-B17 xxxxb R/WB B16 0 2nd Byte ADDRESS (A15-A8) B15-B8 xxh 3rd Byte ADDRESS (A7-A0) B7-B0 xxh xxh Tool,User Program Mode Tool,User Program Mode Tool,User Program Mode User Program Mode only ... DATA (D7-D0) Available Program Mode
Hard Lock Protection Read Protection Sector Erase
1
11b
0000b
0/1
---0, 1110b ---0, 1110b xxh
--11, 1110b --11, 1111b xxh
----, --0-b ----, 0---b ----, ----b
1
11b
0000b
0/1
0
10b
xxxxb
0
18-2
S3C84BB/F84BB
EMBEDDED FLASH MEMORY INTERFACE
FLASH MEMORY CONTROL REGISTERS
Flash Memory Control Register FMCON register is available only in user program mode to program some data to the flash memory.
Flash Memory Control Register (FMCON) FDH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
User Programming Serial Data bit: 0 = FSDAT is Low 1 = FSDAT is High
User Programming Serial Clock bit: 0 = FSCLK is Low 1 = FSCLK is High User Programming Mode Status bit: 0 = Not-user programming mode 1 = user programming mode
Figure 18-1. Flash Memory Control Register (FMCON) Flash Memory User Programming Enable Register RAM Address (00H) of page 8 is used as Flash Memory Enable Register. This location can be addressed by 1-bit or 8-bit instructions. After reset, the user-programming mode is disabled, because the value of FMUSR is "00000000b'. If necessary, you can use the user programming mode by setting the value of FMUSR is "10100101".
Flash Memory User Programming Enable Register (FMUSR) 00H, Page 8, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB
Flash Memory User Programming Enable bits: 00000000 : Disable User Programming Mode 10100101 : Enable User Programming Mode
Figure 18-2. Flash Memory User Programming Enable Register (FMUSR)
18-3
EMBEDDED FLASH MEMORY INTERFACE
S3C84BB/F84BB
The program procedure in User program Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. Set Flash Memory Control Register (FMCON.1) properly to access flash memory Clear FSCLK (FMCON.0) bit, FSDAT (FMCON.7) bit for the initialization of SCLK and SDAT signals Enter into Sector Program Mode with instructions of "LD PP, #88H","LD 00H,#0A5H" orderly. Make SCLK, SDAT signals for start condition with controlling FSCLK, FSDAT bits in FMCON register. Make SCLK, SDAT signals for 3-byte address field with controlling FSCLK, and FSDAT bits in FMCON register. Make SCLK, SDAT signals for data field with controlling FSCLK, and FSDAT bits in FMCON register. Make SCLK, SDAT signals for 1-byte dummy data with controlling FSCLK, and FSDAT bits in FMCON register. Make SCLK, SDAT signals for stop condition by controlling FSCLK, and FSDAT bits in FMCON register. Release User Program Mode with instruction of "LD PP, #88H", and "LD 00H, #00H" orderly.
18-4
S3C84BB/F84BB
EMBEDDED FLASH MEMORY INTERFACE
SECTOR ERASE
User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit of flash memory to be erased and written in User Program Mode is called sector. S3F84BB has 120 sectors to be erased written in flash memory. Sectors have all 512-byte sizes as program memory areas. Sector Erase is not supported in Tool Program Modes (MDS mode). Minimum 2ms to maximum 100ms delay time for erase is required after setting sector address.
Sector 119 (512 Byte)
(HEX) FFFFH FDFFH
writible in user program mode (Flash Program Memory)
Sector 1 (512 Byte) Sector 0 (512 Byte)
13FFH 11FFH 1000H 0FFFH
4-KByte 0000H
Not-writible in user program mode (Flash Program Memory)
Figure 18-3. Sectors in User Program Mode
18-5
EMBEDDED FLASH MEMORY INTERFACE
S3C84BB/F84BB
SDAT SCLK
S 1 2-7 8 9 1 2-7 8 9 1 2-7 8 9 1 2-7 8 9
A23 A22-A17A16Dummy CLK 1'st Byte
A15-A8
Dummy CLK
A7-A0
Dummy CLK
D7-D0
Dummy CLK
2'nd Byte
3'rd Byte
Data = FFH
1st-3rd byte (address field) -010x xxx0b, yyH, zzH The yy, zzH is a sector address
SDAT SCLK
1 2-7 8 9 P
D7-D0 Sector Erase Delay = Typ. 3ms Data = FFH
Dummy CLK
(Dummy data for the time to write last data) Lasr data = always "FF"
Figure 18-4. Sectors Erase Wave Form
18-6
S3C84BB/F84BB
EMBEDDED FLASH MEMORY INTERFACE
PROGRAMMING TIP -- Sector Erase
SB1 CLR SB0 LD LOOPE: NOP LD LD LD SB1 OR TM JR SB0 SB1 OR OR SB0 LD CALL LD CALL LD CALL DELAY: LD DJNZ LD CALL SB1 AND AND SB0 LD LD LD FMCON CLKCON, #00H PP, #88H 00H,#0A5H PP,#00H FMCON,#00000010B FMCON,#00000010B Z, ENT ; clear register ; cpu clock is 16-divide ; ; User Program mode enable ; ; flag enable ; flag check
ENT:
SPGM:
FMCON,#00000001B FMCON,#10000000B R8,#01000000B PGM R8,#00010000B PGM R8,#00000000B PGM R15,#0EBH R15,DELAY R8,#0FFH PGM FMCON,#01111111B FMCON,#11111110B PP,#88H 00H,#00H PP,#00H
; Start ; SCLK=1 ; SDAT=1 ; 1'st Byte (Sector Erase mode) ; 2nd Byte, Address=1000H (Sector 0) ; 3rd Byte ; delay for typical 3ms when 10MHz oscillator used ; ((1/(10MHz/16))x8cycle) x 235 = 3.008 [ms] ; dummy data
; SDAT=0 ; SCLK=0, Stop
; User Program Mode Disable
18-7
EMBEDDED FLASH MEMORY INTERFACE
S3C84BB/F84BB
PROGRAMMING TIP -- Sector Erase (Continued)
REL: SB1 AND TM JR SB0 JP PGM: SB1 AND CALL LD PGMB: RL LDB OR AND DJNZ OR OR SB0 RET WAIT: LOOP0: END_SYM: NOP NOP LD DJNZ RET NOP .END FMCON,#11111101B FMCON,#00000010B NZ, REL END_SYM FMCON,#11111110B WAIT R9, #08H R8 FMCON.7,R8 FMCON,#00000001B FMCON,#11111110B R9, PGMB FMCON,#10000000B FMCON,#00000001B ; Rotate time ; msb -> lsb ; FMCON.7 ; SCLK=1 ; SCLK=0 ; SDAT=1 ; SCLK=1 R8.0 ; flag disable ; flag check
; END ; SCLK=0
R15, #0FFH R15, LOOP0
; 00H <- FFH
18-8
S3C84BB/F84BB
EMBEDDED FLASH MEMORY INTERFACE
PROGRAMMING
A flash memory is programmed in one byte unit after sector erase. The write operation of programming starts at a falling edge of dummy clock when a start address and data have been transmitted, and finishes at a falling edge of last SCLK for next data transmission. The next data to write is transmitted during the previous data is writing. So, S3F84BB has 8-bit buffer register to write data to flash cell and shift register to receive the next data to be written. The address of next data increments automatically at a dummy clock after previous data has been transmitted. Dummy data (FFh) is required after transmission of the last data because the time to write the last data to flash cell is needed. Programming finished when stop condition occurs after the Dummy clock has been transmitted.
SDAT SCLK
S 1 2-7 8 9 1 2-7 8 9 1 2-7 8 9 1 2-7 8 9
A23 A22-A17A16Dummy CLK 1'st Byte
A15-A8
Dummy CLK
A7-A0
Dummy CLK
D7-D0
Dummy CLK
2'nd Byte
3'rd Byte
Data
SDAT SCLK
1 2-7 8 9 1 2-7 8 9 1 2-7 8 9 P
D7-D0
Dummy CLK
D7-D0
D7-D0 Data = FFH
Dummy CLK
Data + n
Data + n +1
(Dummy data for the time to write last data) Lasr data = always "FF"
Figure 18-5. Program Wave Form
18-9
EMBEDDED FLASH MEMORY INTERFACE
S3C84BB/F84BB
PROGRAMMING TIP -- Programming
SB1 CLR SB0 LD LOOPE: NOP LD LD LD SB1 OR TM JR SB0 SB1 OR OR SB0 LD CALL LD CALL LD CALL ADR: FMCON CLKCON, #00H PP, #88H 00H,#0A5H PP,#00H FMCON,#00000010B FMCON,#00000010B Z, ENT ; clear register ; cpu clock is 16-divide ; ; User Program mode enable ; ; flag enable ; flag check
ENT:
SPGM:
FMCON,#00000001B FMCON,#10000000B R8,#01100010B PGM R8,#00010000B PGM R8,#00000000B PGM
; Start ; SCLK=1 ; SDAT=1 ; 1'st Byte (Programming mode) ; 2nd Byte, Address=1000H (Sector 0) ; 3rd Byte ; Write Address = 1000h ~ 10FFh ; Write Data = 66h
LD R3, #00H LD R8, #66H CALL PGM INC R3 JR NZ, ADR LD CALL SB1 AND AND SB0 LD LD LD R8,#0FFH PGM FMCON,#01111111B FMCON,#11111110B PP,#88H 00H,#00H PP,#00H
; dummy data
; SDAT=0 ; SCLK=0, Stop
; User Program Mode Disable
18-10
S3C84BB/F84BB
EMBEDDED FLASH MEMORY INTERFACE
PROGRAMMING TIP -- Programming (Continued)
REL: SB1 AND TM JR SB0 JP PGM: SB1 AND CALL LD PGMB: RL LDB OR AND DJNZ OR OR SB0 RET WAIT: LOOP0: END_SYM: NOP NOP LD DJNZ RET NOP .END FMCON,#11111101B FMCON,#00000010B NZ, REL END_SYM FMCON,#11111110B WAIT R9, #08H R8 FMCON.7,R8 FMCON,#00000001B FMCON,#11111110B R9, PGMB FMCON,#10000000B FMCON,#00000001B ; Rotate time ; msb -> lsb ; FMCON.7 ; SCLK=1 ; SCLK=0 ; SDAT=1 ; SCLK=1 R8.0 ; flag disable ; flag check
; END ; SCLK=0
R15, #0FFH R15, LOOP0
; 00H <- FFH
18-11
EMBEDDED FLASH MEMORY INTERFACE
S3C84BB/F84BB
DATA PROTECTION
Option Sector Programming (Protection option in User Programming Mode) User Program Mode can support Hard lock protection and Read protection when they have not been selected in Tool program mode yet. The data programmed by a user flash memory need to be protected at the fields of application. The flash memory control block in the S3F84BB protects the data with two protection modes: Hardware protection (Hard Lock Protection) Read protection
These protection modes can be enabled by the option selection at a tool program mode or setting the smart option at a user program mode. Hardware Protection (Hard Lock Protection) If this function is enable user or any other thing cannot write and erase the data in a flash memory area. Hard Lock function can be set up in the tool program mode as well as a user program mode. Besides this protection could be released (cleared) by the chip erase execution at a tool program mode. Read Protection There are many users who do not want their code data to be read by any others. Read protection solves this matter by preventing the flash data from being read serially at a tool program mode and is no effective at a user program mode. When this function is enable reading or verifying the flash data at a tool program mode results in zero read out. Read protection can be released (cleared) by the chip erase execution at a tool program mode. NOTES; 1. To enable Hard lock Protection, set the data of address 0E3Eh to "00h" in User Program Mode. 2. To enable Read Protection, set the data of address 0E3Fh to "00h" in User Program Mode.
18-12
S3C84BB/F84BB
EMBEDDED FLASH MEMORY INTERFACE
PROGRAMMING TIP -- Option Sector Programming (Hard Lock Protection in User Program Mode)
SB1 CLR SB0 LD LOOPE: NOP LD LD LD SB1 OR TM JR SB0 SB1 OR OR SB0 LD CALL LD CALL LD CALL LD CALL LD CALL SB1 AND AND SB0 LD LD LD FMCON CLKCON, #00H PP, #88H 00H,#0A5H PP,#00H FMCON,#00000010B FMCON,#00000010B Z, ENT ; clear register ; cpu clock is 16-divide ; ; User Program mode enable ; ; flag enable ; flag check
ENT:
SPGM:
FMCON,#00000001B FMCON,#10000000B R8,#11100000B PGM R8,#00001110B PGM R8,#00111110B PGM R8,#00H PGM R8,#0FFH PGM FMCON,#01111111B FMCON,#11111110B PP,#88H 00H,#00H PP,#00H
; Start ; SCLK=1 ; SDAT=1 ; 1'st Byte (Hard Lock Protection mode) ; 2nd Byte=0E3EH ; 3rd Byte ; Data = 00h(Hard Lock Data) ; dummy data
; SDAT=0 ; SCLK=0, Stop
; User Program Mode Disable
18-13
EMBEDDED FLASH MEMORY INTERFACE
S3C84BB/F84BB
PROGRAMMING TIP -- Option Sector Programming (Hard Lock Protection - Continued)
REL: SB1 AND TM JR SB0 JP PGM: SB1 AND CALL LD PGMB: RL LDB OR AND DJNZ OR OR SB0 RET WAIT: LOOP0: END_SYM: NOP NOP LD DJNZ RET NOP .END Note: It is possible to adopt protection option (read or hard lock protection) in User Program Mode only when it hasn't been adopted by the programmer tools (in Tool Mode before). FMCON,#11111101B FMCON,#00000010B NZ, REL END_SYM FMCON,#11111110B WAIT R9, #08H R8 FMCON.7,R8 FMCON,#00000001B FMCON,#11111110B R9, PGMB FMCON,#10000000B FMCON,#00000001B ; Rotate time ; msb -> lsb ; FMCON.7 ; SCLK=1 ; SCLK=0 ; SDAT=1 ; SCLK=1 R8.0 ; flag disable ; flag check
; END ; SCLK=0
R15, #0FFH R15, LOOP0
; 00H <- FFH
18-14
S3C84BB/F84BB
ELECTRICAL DATA
19
OVERVIEW
ELECTRICAL DATA
In this chapter, S3C84BB/F84BB electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- Input/output capacitance -- D.C. electrical characteristics -- A.C. electrical characteristics -- Oscillation characteristics -- Oscillation stabilization time -- Data retention supply voltage in stop mode -- A/D converter electrical characteristics
19-1
ELECTRICAL DATA
S3C84BB/F84BB
Table 19-1. Absolute Maximum Ratings (TA= 25 C) Parameter Supply voltage Input voltage Output voltage Output current high Output current low Operating temperature Storage temperature Symbol VDD VI VO IOH IOL TA TSTG One I/O pin active All I/O pins active One I/O pin active Total pin current for port Conditions Rating - 0.3 to +6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 +30 +100 - 40 to + 85 - 65 to + 150 C mA Unit V
Table 19-2. D.C. Electrical Characteristics (TA = -25 C to + 85 C, VDD = 2.7 V to 5.5 V) Parameter Operating voltage Input high voltage Symbol VDD VIH1 VIH2 Input low voltage VIL1 VIL2 Conditions fCPU = 10 MHz All input pins except VIH2 XIN All input pins except VIL2 XIN Min 2.7 0.8 VDD VDD-0.5 - - - Typ - - Max 5.5 VDD VDD 0.2 VDD 0.4 Unit V
19-2
S3C84BB/F84BB
ELECTRICAL DATA
Table 19-2. D.C. Electrical Characteristics (Continued) (TA = -25 C to + 85 C, VDD = 2.7 V to 5.5 V) Parameter Output high voltage Symbol VOH1 Conditions VDD = 5 V; IOH = -1 mA All output pins except Port 0,2,6 VDD = 5 V; IOH = -4 mA Port 0,2 VDD = 5 V; IOL = 2 mA All output pins except Port 0,2,6 VDD = 5 V; IOL = 15 mA Port 0,2,6 VIN = VDD All input pins except ILIH2 VIN = VDD XIN VIN = 0 V All input pins except ILIL2 VIN = 0 V XIN VOUT = VDD All I/O pins and Output pins VOUT = 0 V All I/O pins and Output pins VIN = 0 V; VDD = 5 V 10 % Port 0-8, TA = 25C RL2 VIN = 0 V; VDD = 5 V 10% RESET only, TA=25 C 120 240 320 - - 30 - - 46 - - - Min VDD - 1.0 Typ - Max - Unit V
VOH2 Output low voltage VOL1
VDD - 2.0 - 0.12 2.0
VOL2 Input high leakage current ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL RL1
0.6 -
2.0 3 20 -3 -20 5 -5 80 k A
19-3
ELECTRICAL DATA
S3C84BB/F84BB
Table 19-2. D.C. Electrical Characteristics (Concluded) (TA = -25 C to + 85 C, VDD = 2.7 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 IDD2 IDD3 Conditions VDD = 5 V 10 % 10 MHz crystal oscillator Idle mode: VDD = 5 V 10 % 10 MHz crystal oscillator Stop mode: VDD = 5 V 10 % TA = 25 C
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Min -
Typ 8.5 2.5 1
Max 20 5 3
Unit mA
A
19-4
S3C84BB/F84BB
ELECTRICAL DATA
Table 19-3. A.C. Electrical Characteristics (TA = -25 C to +85 C, VDD = 2.7 V to 5.5 V) Parameter Interrupt input high, low width (P4.0-P4.7) (P8.5, P8.6) RESET input low width Symbol tINTH, tINTL tRSL Conditions VDD = 5 V Min 180 Typ - Max - Unit ns
VDD = 5 V
1.0
-
-
s
NOTE: User must keep more large value then min value.
tINTL 0.8 VDD 0.2 VDD
tINTH
0.2 VDD
Figure 19-1. Input Timing for External Interrupts (Ports 4, Port 8.5, Port 8.6)
tRSL RESET 0.2 VDD
Figure 19-2. Input Timing for RESET
19-5
ELECTRICAL DATA
S3C84BB/F84BB
Table 19-4. Input/Output Capacitance (TA = -25 C to +85 C, VDD = 0 V ) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are tied to VSS Min - Typ - Max 10 Unit pF
Table 19-5. Data Retention Supply Voltage in Stop Mode (TA = -25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode VDDDR = 2.0 V, Stop mode Min 2 - Typ - - Max 5.5 3 Unit V A
RESET Occurs Stop Mode Data Retention Mode VDD
Oscillation Stabilization Time Normal Operating Mode
Execution of STOP Instrction RESET 0.2 VDD NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC tWAIT
Figure 19-3. Stop Mode Release Timing Initiated by RESET
~ ~ ~ ~
VDDDR
19-6
S3C84BB/F84BB
ELECTRICAL DATA
Oscillation Stabilization Time Stop Mode Data Retention Mode VDD Idle Mode
Execution of STOP Instruction Interrupt 0.2 VDD tWAIT
~ ~ ~ ~
VDDDR
Normal Operating Mode
NOTE:
tWAIT is the same as 4096 x 16 x BT clock
Figure 19-4. Stop Mode Release Timing Initiated by Interrupts
19-7
ELECTRICAL DATA
S3C84BB/F84BB
Table 19-6. A/D Converter Electrical Characteristics (TA = - 25 C to +85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral Linearity Error Differential Linearity Error Offset Error of Top Offset Error of Bottom Conversion time (1) Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current (2) ILE DLE EOT EOB TCON VIAN RAN AVREF AVSS IADIN IADC 10-bit resolution 50 x 4/fxx, fxx = 10MHz - - - - AVREF = VDD = 5V AVREF = VDD = 5V AVREF = VDD = 3V AVREF = VDD = 5V When Power Down mode AVSS 2 2.5 VSS - - - 1000 - - - 1 0.5 100 AVREF - VDD VSS +0.3 10 3 1.5 500 nA A mA V M V VDD = 5.12 V AVREF = 5.12V AVSS = 0 V fxx = 10 MHz Symbol Conditions Min - - - - - - 20 Typ 10 - - - 1 0.5 - Max - 3 2 1 3 2 - s Unit bit LSB
NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion.
Table 19-7. D/A Converter Electrical Characteristics (TA = - 25 C to +85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Absolute Accuracy Differential Linearity Error Setup Time Output Resistance Symbol - - DLE tSU RO Conditions - Min - -3 -1 - 4.5 Typ - - - - 5 Max 8 3 1 5 5.5 Unit bits LSB LSB s k
19-8
S3C84BB/F84BB
ELECTRICAL DATA
Table 19-8. Flash Memory D.C. Electrical Characteristics (TA = - 25 C to +85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Logic power supply Flash memory operating current (FDD) Symbol VDD FDD1 FDD2 FDD3 VDD = 2.7 V to 5.5 V during reading VDD = 2.7 V to 5.5 V during programming VDD = 2.7 V to 5.5 V during erasing Conditions Min 2.7 - - - Typ 5.0 40 40 40 Max 5.5 80 80 80 Unit V mA mA mA
Table 19-9. Flash Memory A.C. Electrical Characteristics (TA = - 25 C to +85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Programming time(1) Chip Erasing time(2) Sector Erasing time(3) Data access time Number of writing/erasing Symbol Ftp Ftp1 Ftp2 FtRS Fnwe - Conditions VDD = 2.7 V to 5.5 V Min 20 - - - - Typ 30 - 2 50 100 - Max 300 10 Unit uS mS mS mS Times
NOTES: 1. The Programming time is the time during which one byte(8-bit) is programmed. 2. The chip erasing time is the time during which all 64K-byte block is erased. 3. The sector erasing time is the time during which all 60K-byte block is erased.
19-9
ELECTRICAL DATA
S3C84BB/F84BB
Table 19-10. Main Oscillator Frequency (fOSC1) (TA = -25 C to +85 C, VDD = 2.7 V to 5.5 V) Oscillator Crystal Clock Circuit
XIN XOUT
Test Condition Crystal oscillation frequency
Min 1
Typ -
Max 10
Unit MHz
C1
C2
Ceramic
XIN
XOUT
Ceramic oscillation frequency
1
-
10
C1
C2
External clock
XIN
XOUT
XIN input frequency
1
-
10
Table 19-11. Main Oscillator Clock Stabilization Time (tST1) (TA = -25 C to +85 C, VDD = 2.7 V to 5.5 V) Oscillator Crystal Ceramic External clock Test Condition VDD = 2.7 V to 5.5 V Stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input high and low level width (tXH, tXL) Min - - 50 Typ - - - Max 10 4 - ns Unit ms
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a RESET signal.
19-10
S3C84BB/F84BB
ELECTRICAL DATA
1/fOSC1 tXL XIN tXH VDD - 0.5 V 0.4 V
Figure 19-5. Clock Timing Measurement at XIN
Mask type/ Flash type
fCPU 12 MHz 10 MHz
B
4 MHz
A
1 MHz 1 2.7 3 3.3 Supply Voltage (V) Minimum instruction clock = 1/4 x oscillator frequency 4 5 5.5 6 7
Figure 19-6. Operating Voltage Range
19-11
ELECTRICAL DATA
S3C84BB/F84BB
NOTES
19-12
S3C84BB/F84BB
MECHANICAL DATA
MECHANICAL DATA
23.90 ?0.3 20.00 ?0.2 0~8A 0.15 - 0.05
+0.10
17.90 ?0.3
14.00 ?0.2
0.10 MAX
80-QFP-1420C
0.80 ?0.20 #80 (1.00) 0.05 MIN 2.65 ?0.10 0.35 ?0.1 0.15 MAX (0.80) 3.00 MAX #1 0.80 0.80 ?0.20
NOTE: Dimensions are in millimeters.
Figure 20-1. S3C84BB/F84BB 80-QFP Standard Package Dimension (in Millimeters)
20-1
MECHANICAL DATA
S3C84BB/F84BB
14.00BSC 12.00BSC 0~7 0.09~0.20
0.10 MAX 14.00BSC 12.00BSC 0.65 0.15 0.25GAUGE PLANE 0.05~0.15 1.00 0.05 #1 1.20 MAX 0.50 0 .17~0.27 0.08 MAX M (1.25)
80-TQFP-1212-AN
#80
NOTE: Dimensions are in millimeters.
Figure 20-2. S3C84BB/F84BB 80-TQFP Standard Package Dimension (in Millimeters)
20-2
S3C84BB/F84BB
DEVELOPMENT TOOLS
DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with Win95/98/2000 as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+ or SK-1000, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ and SK-1000 is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for In-Circuit Emulator, SHINE (Smart Studio in case of SK-1000), is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SASM ASSEMBLER The SASM88 is a relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters are included with the device-specific target board.
21-1
DEVELOPMENT TOOLS
S3C84BB/F84BB
IBM-PC AT or Compatible
RS-232C
SMDS2+
PROM/OTP Writer Unit
Target Application System
RAM Break/Display Unit Probe Adapter
Bus
Trace/Timer Unit
SAM8 Base Unit
POD
TB84BB Target Board Eva Chip
Power Supply Unit
Figure 21-1. SMDS+ Product Configuration (SK-1000 is single cabinet type)
21-2
S3C84BB/F84BB
DEVELOPMENT TOOLS
TB84BB TARGET BOARD The TB84BB target board is used for the S3C84BB/F84BB microcontroller. It is supported by the SMDS2, SMDS2+, SK-820, or SK-1000 development system.
TB84BB
To User_V CC Off RESET1 On
^[ojXX |X
Stop Idle
+
+
25 J101 1 2 1 J102 2
CN1
40-Pin Connector
|Y
1
39 External Triggers CH1 CH2
40 39
40-Pin Connector 40 SM1XXXA
160 QFP S3E84BB EVA Chip
Figure 21-2. TB84BB Target Board Configuration
GND
VCC
XWWTwG j
21-3
DEVELOPMENT TOOLS
S3C84BB/F84BB
Table 21-1. Power Selection Settings for TB84BB "To User_VCC" Settings
To User_VCC Off On TB84BB VCC VSS VCC SK-1000/SMDS2+ Target System
Operating Mode
Comments The ICE (SK-1000/SMDS2+ ) supplies VCC to the target board (evaluation chip) and the target system.
To User_VCC Off On TB84BB External VCC VSS VCC SK-1000/SMDS2+ Target System
The ICE (SK-1000/SMDS2+) supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
21-4
S3C84BB/F84BB
DEVELOPMENT TOOLS
Table 21-2. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part
External Triggers Ch1 Ch2
Comments
Connector from External Trigger Sources of the Application System
You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) only for the SMDS2+ breakpoint and trace functions.
IDLE LED The Green LED is ON when the evaluation chip (S3E84BB) is in idle mode. STOP LED The Red LED is ON when the evaluation chip (S3E84BB) is in stop mode.
21-5
DEVELOPMENT TOOLS
S3C84BB/F84BB
G:9:
P2.7/TAOUT P2.5/TACK P2.3/DAOUT P2.1/SI P5.7 P5.5 VSS1 N.C P5.4 RESETB P5.1/RxD1 P3.7/TCOUT1 P3.5/T1OUT1 P3.3/T1CAP1 P3.1/T1CK1 P4.7/INT7 P4.5/INT5 P4.3/INT3 P4.1/INT1 P7.7/ADC7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P2.6/TACAP P2.4/TBPWM P2.2/SCK P2.0/SO P5.6 VDD1 N.C N.C(TEST) P5.3/RxD0 P5.2/TxD0 P5.0/TxD1 P3.6/TCOUT0 P3.4/T1OUT0 P3.2/T1CAP0 P3.0/T1CK0 P4.6/INT6 P4.4/INT4 P4.2/INT2 P4.0/INT0 P7.6/ADC6 P7.5/ADC5 AVREF P7.3/ADC3 P7.1/ADC1 P6.7 P6.5 VDD2 P6.3 P6.1 P8.5/INT9 P8.3 P8.1 P1.7 P1.5 P1.3 P1.1 P0.7/PG7 P0.5/PG5 P0.3/PG3 P0.1/PG1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
G:9;
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P7.4/ADC4 AVSS P7.2/ADC2 P7.0/ADC0 P6.6 VSS2 P6.4 P6.2 P6.0 P8.4/INT8 P8.2 P8.0 P1.6 P1.4 P1.2 P1.0 P0.6/PG6 P0.4/PG4 P0.2/PG2 P0.0/PG0
uUjGaGuG
Figure 21-3. 40-Pin Connectors for TB84BB (S3C84BB, 80-QFP Package)
{Gi qXWX [WTwGkpwGj X Y qXWY [X [Y {GjGG[WTwG j wGuaGhz[WkTh vGjaGzt]ZW] Z [W ^ _W
^ _W
Z [W
Figure 21-4. TB84BB Cable for 80-QFP Adapter
21-6
[WTwGkpwG j
[WTwGkpwGj
{Gz qXWY [X [Y qXWX X Y
[WTwGkpwGj
S3C SERIES MASK ROM ORDER FORM
Product description: Device Number: S3C84BB______- ___________(write down the ROM code number) Product Order Form: Package Pellet Wafer Package Type: __________
Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities: Deliverable ROM code Customer sample Risk order Please answer the following questions: See Risk Order Sheet Required Delivery Date - Quantity Not applicable Comments See ROM Selection Form
For what kind of product will you be using this order? New product Replacement of an existing product Upgrade of an existing product Other
If you are replacing an existing product, please indicate the former product name ( )
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Mask Charge (US$ / Won): Customer Information: Company Name: Signatures:
____________________________
___________________ ________________________ (Person placing the order)
Telephone number
_________________________
__________________________________ (Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK
Customer Information: Company Name: Department: Telephone Number: Date: Risk Order Information: Device Number: Package: Intended Application: Product Model Number: S3C________- ________ (write down the ROM code number) Number of Pins: ____________ Package Type: _____________________ ________________________________________________________________ ________________________________________________________________ __________________________ __________________________ Fax: _____________________________
________________________________________________________________ ________________________________________________________________
Customer Risk Order Agreement: We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule: Risk Order Quantity: Delivery Schedule: Delivery Date (s) Quantity Comments _____________________ PCS
Signatures:
_______________________________ (Person Placing the Risk Order)
_______________________________________ (SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C84BB MASK OPTION SELECTION FORM
Device Number: S3C___-________(write down the ROM code number)
Attachment (Check one):
Diskette
PROM
Customer Checksum:
________________________________________________________________
Company Name:
________________________________________________________________
Signature (Engineer):
________________________________________________________________
Please answer the following questions:
Application (Product Model ID: _______________________) Audio CD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom CD Game Office Automation
Please describe in detail its application
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3F84BB SERIES FLASH MCU FACTORY WRITING ORDER FORM (1/2)
Product Description: Device Number: S3F84BB__-________(write down the ROM code number) Package Package Type: Pellet _____________________ Wafer
Product Order Form: If the product order form is package: Package Marking (Check One): Standard
Custom A (Max 10 chars)
Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantity: ROM Code Release Date Required Delivery Date of Device Quantity
Please answer the following questions:
What is the purpose of this order? New product development Replacement of an existing microcontroller Upgrade of an existing product Other
If you are replacing an existing microcontroller, please indicate the former microcontroller name ( )
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same MCU before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Customer Information: Company Name: Signatures: ___________________ ________________________ (Person placing the order) Telephone number _________________________
__________________________________ (Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3F84BB FLASH MCU FACTORY WRITING ORDER FORM (2/2)
Device Number: S3F84BB__-__________ (write down the ROM code number)
Customer Checksums:
_______________________________________________________________
Company Name:
________________________________________________________________
Signature (Engineer):
________________________________________________________________
Read Protection (1):
Yes
No
Please answer the following questions:
Are you going to continue ordering this device? Yes If so, how much will you be ordering? No _________________pcs
Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Other Telecom LCD Game Office Automation
Please describe in detail its application
___________________________________________________________________________
NOTES 1. Once you choose a read protection, you cannot read again the programming code from the ROM. 2. FLASH MCU Writing will be executed in our manufacturing site. 3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

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